Siemens Aktiengesellschaft

Infineon Technologies Ag

Infineon Technologies North America Corp.

Oswald Spindler

Zvonimir Gabric

Jochen C Beintner

Ulrike Gruening

Helmuth Treichel

Dirk Tobben

Alexander Gschwandtner

Gill Lee

Bernhard Neureither

Konrad Hieber

Stephan Wege

Thomas Peter Haneder

Alexander Michaelis

Markus M Kirchhoff

Michael Rogalli

Rainer M Waser

Harald Bachhofer

Hans-Peter Sperlich

Thomas Grassl

Uwe Schilling

Thomas Kruck

Rainer Braun

Jasper Von Tomkewitsch

Doerthe Groteloh

Dirk Toebben

Hans Glawischnig

In a method for producing ferroelectric strontium bismuth tantalate having the composition Sr Bi Ta O (SBT) or Sr Bi (Ta, Nb) O (SBTN), the element strontium, which is normally present in an amount y&equals;2, is provided in excess in a range from 2.1&lE;y&lE;3.0. This makes it possible to carry out the heat treatment step for converting the deposited material into the ferroelectric phase at a temperature T , which is lower than 700&deg; C. In addition, the strontium content x can be reduced from a nominal value of 1 to 0.7.

Low-temperature processing of a ferroelectric strontium bismuth tantalate layer, and fabrication of ferroelectric components using the layer

A method for forming an oxide collar in a trench, in accordance with the present invention, includes forming a trench in a silicon substrate, and depositing and recessing a nitride liner in the trench to expose a portion of the silicon substrate on sidewalls of the trench. An oxide is deposited selective to the nitride liner on the portion of the silicon substrate. Residue oxide is removed from surfaces of the nitride liner to form a collar in the trench.

Collar formation by selective oxide deposition

A method for the shrink-hole-free filling of trenches in semiconductor circuits which utilizes selective growth of a layer to be applied is described. In the method, a layer of a selective growing material is applied simultaneously to a growth-promoting layer and to a growth-inhibiting layer. Wherein raised portions which, before the layer of selective growing material is applied, are covered by the growth-inhibiting layer at least on their sides. After the growth-inhibiting layer has been applied, the growth-promoting layer is generated by anisotropic treatment on surfaces parallel to the substrate on and between the raised portions and the layer is then removed again on surfaces parallel to the substrate on the raised portions. The method makes it possible to produce in a particularly simple manner a pattern on the raised portions of which are covered by the growth-inhibiting layer on their sides and on their top whereas the bottom of trenches is covered with a growth-promoting layer.

Deposition of various base layers for selective layer growth in semiconductor production

A method for controlling isolation layer thickness in trenches for semiconductor devices includes the steps of providing a trench having a conductive material formed therein, forming a liner on sidewalls of the trench above the conductive material, depositing a selective oxide deposition layer on the buried strap and the sidewalls, the selective oxide deposition layer selectively growing at an increased rate on the conductive material than on the liner of the sidewalls and top surface and removing the selective oxide deposition layer except for a portion in contact with the conductive to form an isolation layer on the conductive material in the trench. A method for fabricating vertical transistors by recessing a substrate to permit increased overlap between a transistor channel and buried strap outdiffusion when the transistor is formed is also included. A semiconductor device is also disclosed.

Formation of controlled trench top isolation layers for vertical transistors

A method for depositing a silicon oxide layer by ozone-activated gas phase deposition, uses tetraethyl orthosilicate (TEOS). An initially high gas flow ratio of TEOS to ozone is increasingly varied to a low steady-state ratio.

Method for depositing a silicon oxide layer

When large-scale integrated circuits are produced, pronounced differences in height occur within conductor track levels. Those extreme topographies lead to difficulties during photo-lithographic processes, since there is a direct relationship between resolution and depth of focus. A production method for applying an insulation layer functioning as an intermetal dielectric is based on an ozone-activated selective deposition of silicon oxide. The conductor tracks are completely encapsulated with an insulation layer, so that bulges do not occur above upper edges of the conductor tracks.

Production method for an insulation layer functioning as an intermetal

A method for depositing an SiO.sub.2 layer, which acts as an inter-metal dielectric (IMD), is provided. The method includes the steps of applying to the topography an organodisiloxane which is dissolved in an organic solvent, the organodisiloxane is then polymerized, and the polymer formed is decomposed, the polymer changing in the process to become an SiO.sub.2 -rich layer. The method of the present invention results in SiO.sub.2 layers which achieve an excellent local and global degree of planarization and have a distinctly lower dielectric constant than SiO.sub.2 layers prepared using conventional methods.

Method for forming of a silicon oxide layer on a topography

The method of the present invention provides in a simple manner, the deposition of boron nitride layers with microcrystalline cubic structure which are suitable as insulating layers in VLSI-circuits, as mask membranes in x-ray lithography, as well as coating hard substances. Due to the use of excited starting substances that already contain boron and nitrogen in one molecule and are preferably liquid or solid, and the use of a plasma-CVD-method, the method can be performed using in temperatures of below 500.degree. C. The excitation of the starting substance proceeds preferably in inductive or capacitative fashion in a hollow cathode.

Method for manufacturing microcrystalline cubic boron-nitride-layers

In the ozone-activated deposition of insulating layers, different growth rates can be achieved on differently constituted surfaces. When the surfaces of the structured silicon substrates lying at different levels are differently constituted or, respectively, are intentionally varied such that the SiO.sub.2 insulating layer grows more slowly on the higher surfaces than on the more deeply disposed surfaces and when deposition is carried out until the surfaces of the rapidly growing and slowly growing layer regions form a step-free, planar level, a local and global planarization is achieved.

Method for locally and globally planarizing chemical vapor deposition of

For cleaning parasitic layers of silicon oxides or nitrides in a reaction chamber, an etching gas mixture is employed in which at least one fluoridated carbon, particularly CF.sub.4 and/or C.sub.2 F.sub.6, is the main constituent. Then, an ozone/oxygen mixture (O.sub.3 /O.sub.2) having optimally high ozone concentration is added to the reaction chamber. The etching gas mixture is excited in the reaction chamber by triggering the etching gas mixture to form a plasma, having extremely low power with an excitation frequency in the RF range. The etching gas mixture etches all surfaces in the reaction chambers free of residues with a high etching rate.

Method for cleaning reaction chambers by plasma etching

To create silicon boronitride layers that are utilized as intermetallization layers and/or as final passivation layers, the present invention provides a method wherein fluid initial compounds that already molecularly contain a part of the target composition of the silicon boronitride layer to be produced are utilized, and deposited through chemical vapor deposition in an alternating electromagnetic field. The silicon boronitride layers produced in this fashion have a dielectric constant whose value is below 4 .epsilon..sub.o and are distinguished by good insulating and blocking properties and by a high break down strength.

Growing community of inventors

Vaterstetten, Germany

Oswald Spindler