Mosaid Technologies Corporation

Elbo Inc.

Spawn Labs, Inc.

Satech Group, A.b. Limited Liability Company

Oswald Anthony Becca

Alan S Roth

Peter A Walker

Pedro Ovalle

Robert McKenzie

Jody Defazio

Peter Nyasulu

A system for allowing a user to remotely access a game includes: a game console; a remote console client configured to receive a game control signal; and a remote console server. The remote console server includes an audio and video encoder configured to receive an audio output and a video output from the game console and to convert the audio output and the video output to a network packet. The remote console server also includes: a game controller emulation unit and a network interface configured to send and receive the network packet. The game controller emulation unit is configured to receive a game controller signal from the game console and to send the game controller signal to the remote console client and to receive a game controller input from the remote console client and send the game controller input to the game console.

System for remote game access

A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.

Double data rate output circuit

Double data rate output circuit and method

In a memory interface, a delay locked loop (DLL) is added to the system in order to provide an accurate, PVT insensitive translation of the drive clocks into the write data eye. Adding a master-slave DLL to the system provides an accurate, PVT insensitive translation of the echo clocks into the read data eye. Solidifying the timing critical drive and receive logic which directly interfaces to the I/O buffers reduces the pin-to-pin skews. Utilizing clock phase outputs of the DLL in the solidified drive and receive logic blocks reduces further the skew between the clock and related data signals, and also removes the reliance on a differential clock. The system allows a much more relaxed constraint on clock duty cycle. Design of circuitry within the solidified drive and receive logic blocks permits simple logic modeling for fit within an ASIC flow. Physical design of the solidified drive and receive logic blocks permits simple fit within ASIC place and route flows for increased ease of implementation and ease of reuse.

Double data rate converter circuit includes a delay locked loop for providing the plurality of clock phase signals

Double data rate output latch for static RAM device has edge-triggered flip-flop to output DDR signal to synchronize with a second clock signal

A delay locked loop (DLL) is added to the system in order to provide an accurate, PVT insensitive translation of the drive clocks into the write data eye. Adding a master-slave DLL to the system provides an accurate, PVT insensitive translation of the echo clocks into the read data eye. Solidifying the timing critical drive and receive logic which directly interfaces to the I/O buffers reduces the pin-to-pin skews. Utilizing clock phase outputs of the DLL in the solidified drive and receive logic blocks reduces further the skew between the clock and related data signals, and also removes the reliance on a differential clock. The system allows a much more relaxed constraint on clock duty cycle. Design of circuitry within the solidified drive and receive logic blocks permits simple logic modeling for fit within an ASIC flow. Physical design of the solidified drive and receive logic blocks permits simple fit within ASIC place and route flows for increased ease of implementation and ease of reuse.

Apparatus and method for interfacing to a memory

Synchronization circuit and method with transparent latches

A system and method for searching and deleting segmented wide word entries in a CAM array is disclosed. A normal CAM search operation is executed to find the first word segment of a wide word. Once found, a search and delete operation is executed to find all successive word segments of the wide word, with the last word segment being marked as a deleted word segment, along a first CAM array direction. Once the last word segment is deleted, the wide word is considered to have been deleted because subsequent searches for the wide word will not find its last word segment. A purge operation is then executed along the opposite CAM array direction to delete all the word segments of the deleted wide word. Match processing circuits in each row of the CAM array can pass search results to an adjacent row above or below it to ensure that only word segments belonging to the wide word are found in the search and delete operation and deleted in the purge operation.

Method and apparatus for wide word deletion in content addressable memories

A CAM system comprising a plurality of CAM devices connected in a serial cascade arrangement, the CAMs in the cascade being connected to an adjacent CAM by a respective forwarding bus, with at most a first CAM in the cascade being connected to a receive data signals from a host controller and at most a last CAM devices being coupled to forward results back to the host controller; and a send signal generation means for supplying a SEND signal to the last CAM; the SEND signal for coordinating transfer of the search result from the last CAM to the host controller, the serial cascade arrangement minimizing the number of CAMs being connected to a common forwarding bus.

Growing community of inventors

Round Rock, TX, United States of America

Oswald Anthony Becca