Oracle America, Inc.

Oracle International Corporation

Osman Javed

Dawei Huang

Drew George Doblar

Deqiang Song

Zuxu Qin

Dong Joon Yoon

Waseem Ahmad

Nirmal Chindhu Warke

Jianghui Su

Andrew Keith Joy

William Franklin Leven

Hongtao Zhang

Daniel J Beckman

Simon Dennis Forey

In a receiver circuit, a node receives a signal that carries data from a transmitter circuit. Moreover, a clock-data-recovery (CDR) circuit in the receiver circuit recovers an at-rate clock signal from the received signal. The CDR circuit recovers the clock signal without converging a first pulse-response precursor of the signal relative to a pulse-response cursor of the signal to approximately zero (e.g., with the first pulse-response precursor h(&#x2212;1) converged to a non-zero value). Furthermore, the first pulse-response precursor corresponds to at least one precurosor or postcursor of the pulse-response other than the current sample.

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A feedback module is defined to receive as input a set of data sample signals and a set of reference sample signals. Each of the data and reference sample signals is generated by sampling a differential signal having been transmitted through a FIR filter. The feedback module is defined to operate a respective post cursor counter for each post cursor of the FIR filter and update the post cursor counters based on the received sets of data and reference sample signals. Also, the feedback module is defined to generate a tap weight adjustment signal for a given tap weight of the FIR filter when a magnitude of a post cursor counter corresponding to the given tap weight is greater than or equal to a threshold value. An adaptation module is defined to adapt a reference voltage used to generate the reference sample signals to a condition of the differential signal.

Real-time optimization of TX FIR filter for high-speed data communication

An analog baud rate clock and data recovery apparatus includes a first track and hold circuit that delays a received signal by one unit interval to create an odd signal; a second track and hold circuit that delays the received signal by one unit interval to create an even signal; a first comparator circuit; and a second comparator circuit. The first track and hold circuit outputs the odd signal to the first comparator circuit and the second comparator circuit. The second track and hold circuit outputs the even signal to the first comparator circuit and the second comparator circuit. The first comparator adds the odd signal to the even signal and outputs a first potential timing error. The second comparator subtracts the odd signal and the even signal and outputs a second potential timing error signal. A desired timing error signal is derived from the first and second potential timing error signals. The desired timing error signal is used to determine whether signal sampling is early or late.

Analog baud rate clock and data recovery

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Sunnyvale, CA, United States of America

Osman Javed