Imec

Samsung Electronics Co., Ltd.

Osman Allam

Suk Jin Kim

Patrick Merken

Francesco Cannillo

Bingfeng Mei

Munir Abdalla Mohamed

A hardware memory architecture or arrangement suited for multi-processor systems or arrays is disclosed. In one aspect, the memory arrangement includes at least one memory queue between a functional unit (e.g., computation unit) and at least one memory device, which the functional unit accesses (for write and/or read access).

Memory arrangement for multi-processor systems including a memory queue

A circuit and method for providing a digital output indicative of the time at which an event occurred is disclosed. In one aspect, the circuit includes a fine timing circuit configured to determine in which sub-interval of a clock period the event occurred, and a correction circuit configured to correct an erroneous offset between a first and second clock signals in the fine timing circuit. The correction circuit includes a synch circuit configured to determine in which half of the clock period the event occurred so as to correct for erroneous offset in the fine timing circuit.

Time stamp generation

Growing community of inventors

Leuven, Belgium

Osman Allam