Arm Limited

Oskar Lars Flordal

Jorn Nystad

Andreas Due Engh-Halstvedt

Ola Hugosson

Jakob Axel Fries

Jeremy Davies

Daren Croxford

Simon James Jones

Sharjeel Saeed

Ian Victor Devereux

Hakan Persson

Henrik Nils-Sture Olsson

David James Bermingham

An interface apparatus and method of operating the same are provided. The interface apparatus receives an uncompressed image data read request using a first addressing scheme at a first bus interface and transmits a compressed image data read request using a second addressing scheme from a second bus interface. Address translation circuitry translates between the first addressing scheme and the second addressing scheme. Decoding circuitry decodes a set of compressed image data received via the second bus interface to generate the set of uncompressed image data which is then transmitted via the first bus interface. The use of a second addressing scheme and image data compression is thus transparent to the source of the uncompressed image data read request, and the interface apparatus can therefore be used to connect devices which use different addressing schemes and image data formats, without either needing to be modified.

Interface apparatus and method of operating an interface apparatus

A data processing system includes a processing pipeline for the parallel execution of a plurality of threads. An issue controller issues threads to the processing pipeline. A stall manager controls the stalling and unstalling of threads when a cache miss occurs within a cache memory. The issue controller issues the threads to the processing pipeline in accordance with both a main sequence and a pilot sequence. The pilot sequence is followed such that threads within the pilot sequence are issued at least a given time ahead of their neighbors within a main sequence. The given time corresponds approximately to the latency associated with a cache miss. The threads may be arranged in groups corresponding to blocks of pixels for processing within a graphics processing unit.

Thread issue control

A processing system comprises plural processing cores and a task allocator for allocating tasks to the processing cores. The processing cores perform the tasks that are allocated to them so as to produce results for the tasks, the results being stored by the processing cores in a buffer. The task allocator indicates to the processing cores memory portions within the buffer in which to store the results. When the processing cores determine that a given memory portion is becoming full, the processing cores request that the task allocator indicates a new memory portion in which to store its results. The processing system allows the task allocator to dynamically and efficiently allocate memory portions to plural processing cores without the task allocatorneeding to know the sizes of the results being produced by the processing cores.

Memory allocation in a multi-core processing system based on a threshold amount of memory

Image data is subject to compression and decompression when it is respectively written to and read from a frame buffer. If a portion of the image data is identified as static (subject to less than a threshold amount of change for greater than a threshold time), then compression control parameters used for compression of that portion of the image are adjusted so as to increase the compression ratio achieved, hold the degree of lossiness substantially constant and increase the energy consumed while compressing that portion. The increased energy consumption during this high compression ratio compression is likely compensated for by a reduction in energy subsequently consumed when writing that frame-buffer image data to the frame buffer and reading that frame-buffer image data multiple times from the frame buffer. The compression characteristics varied may be to increase the block size used in the compression. Other variations in compression applied may be to change from single-pass compression to multi-pass compression, switch compression on and off altogether, or reorder the data when it has been compressed so as to match the order it will be read and so achieve support for longer read burst.

Adaptive frame buffer compression

A tile-based graphics processing systemhas a write out stageconfigured to compress depth data by dividing each depth value to be compressed into plural parts, forming plural depth data channels by associating corresponding ones of the plural parts of different depth values with each other and applying a data compression scheme separately to each depth data channel to be compressed in order to produce compressed representations of the depth data channels. The compressed representations of the depth data channels are written to external memory

Methods of and apparatus for compressing depth data

A data arrayto be stored is first divided into a plurality of blocks. Each blockis further sub-divided into a set of sub-blocks, and a set of data for each sub-blockis then stored in a body data buffer. A header data blockis stored for each blockat a predictable memory address within a header buffer. Each header data block contains pointer data indicating the position within the body bufferwhere the data for the sub-blocks for the blockthat that header data blockrelates to is stored, and data indicating the size of the stored data for each respective sub-block

Methods of and apparatus for storing data in memory in data processing systems

To encode and compress a data array, the data arrayis first divided into a plurality of blocks. A quadtree representation is then generated for each blockby initializing each leaf node of the quadtree to the value of the data element of the blockof the data arraythat the leaf node corresponds to, and initializing each non-leaf node to the minimum value of its child nodes, and then subtracting from each node except the root node the value of its parent node. A set of data indicating the differences between respective parent and child node values in the quadtree representing the block of the data array is then generated and stored, together with a set of data representing a quadtree indicating the number of bits that have been used to signal the respective difference values.

Methods of and apparatus for encoding and decoding data in data processing systems

Methods of and apparatus for using tree representations for representing arrays of data elements for encoding and decoding data in data processing systems

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Lund, Sweden

Oskar Lars Flordal