Siemens Aktiengesellschaft

Infineon Technologies Ag

Siemens Aktiengesell Schaft

Siemens Aktiengelsellschaft

Oskar Kowarik

Kurt Hoffmann

Rainer Kraus

Manfred Paul

Hans-Dieter Oberle

Georg Braun

Heinz H&ouml;nigschmid

Bernhard Lustig

Franz Schuler

Thomas R&ouml;hr

Johannes Stecker

Andreas Graf Von Schwerin

Hans D Oberle

Kurt Hoffman

Klaus Luther

An evaluation configuration has a first MOS evaluation stage, an isolation stage, and a bipolar evaluation stage. The isolation stage is connected between the first MOS evaluation stage and the bipolar evaluation stage. The isolation stage isolates the first MOS evaluation stage from the bipolar evaluation stage. The evaluation configuration can reliably detect very small read signals and allows a high integration density.

Evaluation configuration for semiconductor memories

A DRAM memory cell having an isolation transistor formed from a bipolar transistor.

Semiconductor memory device

A circuit is provided for the non-destructive, self-normalizing reading-out of MRAM memory cells. Accordingly, read currents of a memory cell are normalized by currents that are maintained at a voltage at which the size of these currents is independent of the cell content. The circuit has a simple construction and without great expenditure, permits the normalization of a read signal.

Circuit for non-destructive, self-normalizing reading-out of MRAM memory cells

A resistive ferroelectric memory cell includes a selection transistor having first and second zones of a first conduction type. A storage capacitor has one electrode at a fixed cell-plate voltage and another electrode connected to the first zone of the selection transistor. A semiconductor substrate has a second conduction type opposite the first conduction type. The storage capacitor and the selection transistor are disposed in the semiconductor substrate. A resistor is disposed between the other electrode of the storage capacitor and the fixed cell-plate voltage. The resistor has a resistance R such that R <<R <<R , in which R is a reverse resistance of a pn junction between the first zone of the selection transistor and the semiconductor substrate and R is a resistance between the first zone and the second zone of the selection transistor, in a turned-on state.

Resistive ferroelectric memory cell

A semiconductor circuit is disclosed which contains a driving circuit which is integrated into a semiconductor substrate of a first conductivity type and includes positive voltage switching transistors for switching positive and/or zero voltage levels and negative switching transistors for switching negative and/or zero voltage levels. In addition, the driving circuit contains a control circuit which is positioned upstream from the driving circuit and is also embodied in the semiconductor substrate, which is connected to a substrate voltage. A negative voltage switching transistor of the driving circuit is configured inside an outer well which is embedded in the semiconductor substrate and is of a second conductivity type which is opposite to the first, and the outer well is connected to a supply voltage.

Semiconductor circuit configuration

A memory configuration includes a plurality of resistive ferroelectric memory cells. Each of the memory cells includes a selection transistor and a storage capacitor. The selection transistor has a given zone of a first conductivity type. The storage capacitor has a first and a second electrode. The first electrode is supplied with a fixed cell plate voltage, the second electrode is connected to the given zone of the first conductivity type. A source and a drain of a MOS transistor are supplied with the fixed cell plate voltage. The channel of the MOS transistor has a channel length extending over at least two of the memory cells. The given zone of the first conductivity type is connected, via a resistor, to the channel of the MOS transistor such that the given zone is electrically connected to the first electrode of the storage capacitor via the resistor and the MOS transistor.

Memory configuration including a plurality of resistive ferroelectric memory cells

A method for reading non-volatile semiconductor memory configurations includes determining a high threshold voltage and a low threshold voltage based on a charge state of a floating gate for a transistor, and applying a reverse bias between a bulk and a source of the transistor during reading.

Method for reading nonvolatile semiconductor memory configurations

A memory configuration includes a plurality of resistive ferroelectric memory cells. Each of the resistive ferroelectric memory cells includes a selection transistor and a storage capacitor. The selection transistor has a given zone of a first conductivity type. The storage capacitor has a first electrode and a second electrode. The first electrode is supplied with a fixed cell plate voltage. The second electrode is connected to the given zone of the first conductivity type. A semiconductor body of a second conductivity type opposite the first conductivity type is provided. A line is formed by a highly doped zone of the first conductivity type. The line is supplied with the cell plate voltage. The second electrode of the storage capacitor is connected via the resistor to the line.

A circuit for generating a reference voltage for the reading out from and the evaluation of read output signals which are read out with a constant plate voltage from storage cells of a ferroelectric memory via bit lines. In the circuit, a reference voltage device is formed of two reference cells that are subjected to the action of complementary signals. The reference cells can be simultaneously read out in order to generate the reference voltage in a selection and evaluation device.

Circuit configuration for generating a reference voltage for reading a ferroelectric memory

A method for nondestructively reading memory cells of an MRAM memory, which includes steps of: determining a standard resistance of a memory cell at a voltage at which a resistance of the memory cell is independent of a stored content of the memory cell; determining an actual resistance of the memory cell at a voltage at which the resistance of the memory cell is dependent on the stored content of the memory cell; obtaining a normalized actual resistance of the memory cell by dividing the actual resistance by the standard resistance; obtaining a comparison result by comparing the normalized actual resistance with a reference value; and detecting the stored content of the memory cell dependent on the comparison result.

Method for nondestructively reading memory cells of an MRAM memory

A configuration for self-referencing a ferroelectric memory cell reads out the ferroelectric memory cell successively while a bit line is precharged to two different, opposing voltages. The voltage values read out from the ferroelectric memory cell are temporarily stored respectively in a first and a second capacitor and then fed to an evaluator circuit.

Configuration for self-referencing ferroelectric memory cells

An integrated buffer circuit includes a first series circuit connected between a first supply potential and a second supply potential (ground). The first series circuit has a voltage-controlled first constant current source, a first field effect transistor having a gate forming an input of the buffer circuit, a circuit node between the first current source and the first field effect transistor forming an output of the buffer circuit, and a first control input for controlling the first current source with a reference potential having a constant potential difference relative to the first supply potential. A second series circuit is connected between the first supply potential and the second supply potential. The second series circuit has a first resistor, a second constant current source furnishing a current being independent of the first supply potential, and a circuit node between the first resistor and the second current source, establishing the reference potential and being connected to the first control input of the first current source.

Integrated buffer circuit which functions independently of fluctuations

An integrated semiconductor circuit includes word lines and bit lines. A memory region has at least one memory cell field with memory cells addressable through the word lines and the bit lines, and a number of evaluator circuits corresponding to the number of the bit lines. Each of the evaluator circuits is connected with one of the bit lines and divides the one bit line into two at least approximately identical bit line halves. Logic units of a block perform digital processing of data read-out of the memory region through the bit lines and evaluated. Each of the logic units is connected to the two bit line halves of one of the bit lines. Various operating modes of the block of logic units are selected with mode select signals.

Integrated semiconductor circuit

An integrated semiconductor memory includes a memory cell field having memory cells disposed in matrix form, word lines and internal bit lines forming pairs of internal bit lines for triggering the memory cells. Internal weighting circuits are each assigned to a respective one of the internal bit line pairs. An external pair of bit lines is commonly assigned to the internal bit lines. Pairs of separation transistors are each assigned to a respective one of the internal bit line pairs for electrical separation of the respective internal bit line pair from the external pair of bit lines. A bit line decoder triggers the pairs of separation transistors. An external weighting circuit is provided. A discriminator device and a precharging device are connected to the external bit line pair. The internal bit lines of each pair of internal bit lines are triggered separately from one another. The internal bit lines of each pair of internal bit lines are connected to the external bit line pair separately from one another.

Integrated semiconductor memory

An integrated semiconductor memory of the DRAM type includes word lines and bit line pairs. Memory cells in a matrix are connected to the word lines and the bit lines. One evaluator circuit per bit line pair is connected to the bit lines. Each of the bit line pairs is divided into one bit line and one reference bit line during operation. A control line is provided. At least one coupling capacitor is provided for each of the bit lines and each of the reference bit lines having a first lead connected to the bit line pair and a second lead connected to the control line. A method for testing an integrated semiconductor memory of the DRAM type includes reading data stored in memory cells out of the memory cells, precharging bit line pairs to a precharge level before reading out, and feeding an additional potential to each bit line pair after precharging.

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Neubiberg, Germany

Oskar Kowarik