International Business Machines Corporation

Elpis Technologies Inc.

Globalfoundries Inc.

Oscar Van Der Straten

Alexander Reznicek

Praneet Adusumilli

Chih-Chao Yang

Koichi Motoyama

Joseph F Maniscalco

Keith E Fogel

Michael Rizzolo

Kenneth Chun Kuen Cheng

Adra Carr

Ruilong Xie

Joshua M Rubin

Scott A DeVries

Hemanth Jagannathan

Ashim Dutta

James John Kelly

Shanti Pancharatnam

Kangguo Cheng

Juntao Li

Carl John Radens

Bahman Hekmatshoartabari

Theodorus E Standaert

Tak H Ning

Oleg Gluschenkov

Christopher J Penny

Sufi Zafar

Terry Allen Spooner

James J Demarest

Miaomiao Wang

Willie Lester Muchrison, Jr

Lisamarie White

Bruce Bennett Doris

Choonghyun Lee

Daniel C Edelstein

Balasubramanian Pranatharthiharan

Hariklia Deligianni

Zuoguang Liu

Yann Mignot

Sandra Guy Malhotra

John Anthony Fitzsimmons

Seyoung Kim

Stephen Mark Rossnagel

Muthumanickam Sankarapandian

David Lee Rath

Cornelius Brown Peethala

Shyng-Tsong Chen

Vimal Kumar Kamineni

Raghuveer Reddy Patlolla

Chao-Kun Hu

Xiaoyan Shao

Tsung-Sheng Kang

Dominik Metzler

Dimitri Houssameddine

Gangadhara Raja Muthinti

Eric Raymond Evarts

Virat Vasav Mehta

Tsong-Lin Tai

Kenneth C K Cheng

Arthur Gasasira

A semiconductor structure includes a backside power rail disposed in a backside dielectric layer, and dielectric spacer layers laterally extending inwardly from opposing sidewalls of the backside dielectric layer and on a portion of a bottom surface of the backside power rail.

Power distribution network with backside power rail

A method to form a semiconductor structure for a magnetoresistive random-access memory (MRAM) device where the material for the top electrode and the bottom electrode is deposited in a single process. The method includes conformally depositing an electrode material over a magnetic tunnel junction (MTJ) pillar, under the MTJ pillar, around a spacer encapsulating and extending above the MTJ pillar. The method includes recessing the electrode material to form a thinner portion of the electrode material over the MTJ pillar. The thinner portion of the electrode material forms a thinner portion of the electrode material over the MTJ pillar that is a top electrode. The portion of the electrode material under the MTJ pillar forms a bottom electrode that is thicker than the top electrode.

Magnetoresistive random-access memory with top and bottom electrodes deposited in unison

A wire interconnect, a wire interconnect structure, and a method to form wire interconnect structures with locally widened profiles. The wire interconnect may include a first portion of the wire interconnect with a first width. The wire interconnect may also include a second portion of the wire interconnect with a second width, where the second width is greater than the first width, and where the second portion of the wire interconnect is above the first portion of the wire interconnect. The wire interconnect may also include a third portion of the wire interconnect with a third width, where the third width is less than the second width, and where the third portion of the wire interconnect is above the second portion of the wire interconnect.

Locally widened profile for nanoscale wiring structure

Embodiments of present invention provide a method of forming a MRAM structure. The method includes forming a bottom electrode layer surrounded by a bottom dielectric layer; forming an etch-stop layer on top of the bottom electrode layer and the bottom dielectric layer; creating an opening in the etch-stop layer to expose a top surface of the bottom electrode layer; forming a first ferromagnetic layer on top of the bottom electrode layer and the etch-stop layer, with a portion of the first ferromagnetic layer filling the opening in the etch-stop layer; forming a tunnel barrier layer and a second ferromagnetic layer on top of the first ferromagnetic layer; patterning the second ferromagnetic layer, the tunnel barrier layer, and the first ferromagnetic layer; and forming a top electrode layer on top of the second ferromagnetic layer. A structure formed thereby is also provided.

MRAM structure with a T-shaped ferromagnetic layer

A magnetic tunnel junction cell, a cross section with octagon profile, vertically aligned layers of a top electrode, a free layer, a tunneling barrier, a reference layer, a bottom electrode with tapered side surface with a width at an upper surface greater than a width at a lower surface, the reference layer with vertical side surface perpendicular to an upper horizontal surface of the bottom electrode, the free layer and the tunneling barrier, each include a tapered side surface of the same angle, and each include a width at an upper surface less than a width at a lower surface. Forming a bottom electrode of a magnetic tunnel junction cell with a tapered side surface with a width at an upper surface greater than a width at a lower surface, forming a reference layer with vertical side surface perpendicular to an upper surface of the bottom electrode.

MRAM device with octagon profile

A memory device includes a magnetic tunnel junction pillar above a bottom electrode. A sidewall spacer is disposed along sidewalls of the magnetic tunnel junction pillar with an uppermost surface of the sidewall spacer being coplanar with an uppermost surface of the magnetic tunnel junction pillar. A dielectric hardmask composed of an amorphous dielectric material is disposed above a first portion of the uppermost surface of the magnetic tunnel junction pillar, the dielectric hardmask includes a hemispherical shape. A top electrode is located surrounding the dielectric hardmask and above the uppermost surface of the sidewall spacer and a second portion of the uppermost surface of the magnetic tunnel junction pillar extending outwards from the dielectric hardmask.

Magneto-resistive random access memory with hemispherical top electrode

A magnetic tunnel junction (MTJ) stack, a vertical side surface of the MTJ stack includes a saw tooth edge, the MTJ stack includes vertically aligned layers of a top electrode, a free layer, a tunneling barrier, a reference layer and a bottom electrode, the free layer of the MTJ stack has a tapered edge including a first width at an upper portion of the free layer and a second width at a lower portion of the free layer, the first width is greater than the second width. Forming a first bottom electrode of a first MTJ stack, a second bottom electrode of a second MTJ stack, a first inter-layer dielectric between the first and the second bottom electrode, a first reference layer of the first MTJ stack, a second reference layer of the second MTJ stack, a second inter-layer dielectric between the first reference layer and the second reference layer.

Damascene MRAM device

An MRAM device is provided. The MRAM device includes a first electrode, an MRAM stack formed on the first electrode, a hardmask structure formed on the MRAM stack, and a second electrode formed on the hardmask structure. A width of an upper portion of the hardmask structure is less than a width of the MRAM stack.

Conical magnetic random access memory pillar structures

Embodiments of present invention provide a method of forming a MRAM structure. The method includes forming a magnetic tunnel junction (MTJ) stack; forming a first dielectric layer to a level above a tunnel barrier layer of the MTJ stack, the first dielectric layer partially covering the MTJ stack with a top surface of the MTJ stack being exposed; depositing an etch-stop layer covering the top surface of the MTJ stack and a top surface of the first dielectric layer; depositing a second dielectric layer covering the etch-stop layer; forming an opening in the second dielectric layer; removing a portion of the etch-stop layer above the top surface of the MTJ stack; and forming a top contact by depositing a conductive material in the opening. An MRAM structure formed thereby is also provided.

MRAM device structure

Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A first set of spacers are formed on the sidewalls of a bottom electrode. A reference layer is formed on the spacers and the bottom electrode. A second set of spacers are formed on the sidewalls of the first set of spacers and the reference layer. A tunnel barrier is formed on the reference layer and the second set of spacers. A free layer is formed on the tunnel barrier, where a width of the free layer is greater than a width of the reference layer. A metal hardmask is formed on the free layer. A third set of spacers are formed on the sidewalls of the metal hardmask, the free layer, the tunnel barrier, and the second set of spacers.

Etching of magnetic tunnel junction (MTJ) stack for magnetoresistive random-access memory (MRAM)

A semiconductor structure may include a pyramidal magnetic tunnel junction on top of a bottom electrode, a tunnel layer on top and in electrical contact with the first magnetic layer, a second magnetic layer on top and in electrical contact with the tunnel layer, and a hard mask cap on top of the second magnetic layer. The pyramidal magnetic tunnel junction may have a first magnetic layer on top and in electrical contact with the bottom electrode. The semiconductor structure may include a first encapsulation spacer positioned along vertical sidewalls of the hard mask cap, a second encapsulation spacer positioned along vertical sidewalls of the second magnetic layer, a third encapsulation spacer positioned along vertical sidewalls of the tunnel layer, and a fourth encapsulation spacer positioned along vertical sidewalls of the first magnetic layer.

MRAM structure with multilayer encapsulation

A magneto-resistive random access memory with segmented bottom electrode includes a magnetic tunnel junction pillar above a first portion of a bottom electrode layer, the first portion of the bottom electrode layer includes a metal region. A sidewall spacer is disposed along sidewalls of the magnetic tunnel junction pillar and above a second portion of the bottom electrode layer including a metal-oxide region. The first portion of the bottom electrode layer composed of the metal region and the second portion of the bottom electrode layer composed of the metal-oxide region form the segmented bottom electrode.

Magneto-resistive random access memory with segmented bottom electrode

A memory device with modified top electrode contact includes a memory pillar composed of a bottom electrode, a magnetic random-access memory (MRAM) stack above the bottom electrode, and a top electrode above the MRAM stack. A first portion of an encapsulation layer is disposed along opposite sidewalls of the bottom electrode, on opposite sidewalls of the MRAM stack and on opposite sidewalls of a bottom portion of the top electrode, a second portion of the encapsulation layer is located above a second dielectric layer. A metal cap is located above an uppermost surface and opposite sidewalls of a top portion of the top electrode and above an uppermost surface of the first portion of the encapsulation layer. A second conductive interconnect is formed above a top surface of the metal cap wrapping around opposite sidewalls of the first portion of the encapsulation layer and opposite sidewalls of the metal cap.

Modified top electrode contact for MRAM embedding in advanced logic nodes

A magnetic tunnel junction pillar is positioned above a bottom electrode composed of a metal-oxide region in contact with a first portion of the magnetic tunnel junction pillar and a metal region surrounding the metal-oxide region. A sidewall spacer is positioned along sidewalls of the magnetic tunnel junction pillar, and the metal region is in contact with a bottom surface of the sidewall spacer and a second portion of the magnetic tunnel junction pillar.

Magneto-resistive random access memory with substitutional bottom electrode

A ring-shaped heater, system, and method to gradually change the conductance of the phase change memory through a concentric ring-shaped heater. The system may include a phase change memory. The phase change memory may include a bottom electrode. The phase change memory may also include a ring-shaped heater patterned on top of the bottom electrode, the ring-shaped heater including: a plurality of concentric conductive heating layers, and a plurality of insulator spacers, where each insulator spacer separates each conductive heating layer. The phase change memory may also include a phase change material proximately connected to the ring-shaped heater. The phase change memory may also include a top electrode proximately connected to the phase change material.

Phase change memory with concentric ring-shaped heater

Growing community of inventors

Guilderland Center, NY, United States of America

Oscar Van Der Straten