Globalfoundries U.S. Inc.

Globalfoundries Singapore Pte. Ltd.

Oscar Restrepo

Yusheng Bian

Vibhor Jain

John Joseph Pekarik

Alexander M Derrickson

Rui Tze Toh

Anupam Dutta

Ping-Chuan Wang

Zhong-Xiang He

Theodore James Letavic

Bartlomiej Jan Pawlak

William James Taylor, Jr

Edmund Kenneth Banghart

Hemant M Dixit

Koushik Ramachandran

Ajay Raman

Rainer Thoma

Vvss Satyasuresh Choppalli

William Taylor

Brian McGowan

Eduardo Cruz Silva

V V S S Satyasuresh Choppalli

A structure includes a transistor, e.g., HEMT, with a field plate positioned laterally to a side of an active gate and including a first portion extending over the active gate. A dielectric layer isolates a lower surface of the first portion from an upper surface of the active gate. A field plate contact includes interconnect layers located directly over the active gate and electrically coupled to the first portion directly over the active gate. The field plate contact allows electrical operation of the field plate, but also acts as a thermally conductive path from the active gate through the interconnect layers to cool likely hot spots within the transistor.

Field plate structure to reduce self-heating in transistor and related method

Structures including an edge coupler and methods of forming such structures. The structure comprises a dielectric layer on a semiconductor substrate. The dielectric layer includes a cavity and an edge defining a boundary of the cavity. The structure further comprises an edge coupler including a waveguide core. The waveguide core includes a portion that extends past the edge of the dielectric layer and overhangs the cavity. The structure further comprises a heater positioned adjacent to the portion of the waveguide core. The heater is spaced by a gap from the portion of the waveguide core.

Edge couplers with a fine-alignment mechanism

A semiconductor device includes a first substrate, a second substrate bonded to the first substrate, and at least one thermally conductive structure that extends through a portion of the first substrate and a portion of the second substrate and is vertically aligned with an active region of the first substrate. The at least one thermally conductive structure is electrically insulated from electrically active structures in the semiconductor device. The thermally conductive structure acts as a heat sink to transfer heat from the active region.

Heat sink for face bonded semiconductor device

Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises an intrinsic base including a first semiconductor layer, a collector including a second semiconductor layer, and an emitter including a third semiconductor layer. The first semiconductor layer, which comprises silicon-germanium, includes a first portion and a second portion adjacent to the first portion. The second semiconductor layer includes a portion on the first portion of the first semiconductor layer, and the third semiconductor layer includes a portion on the second portion of the first semiconductor layer. The structure further comprises a dielectric spacer laterally between the portion of the second semiconductor layer and the portion of the third semiconductor layer.

Heterojunction bipolar transistors with terminals having a non-planar arrangement

Structures for a thermo-optic phase shifter and methods of forming such structures. The structure comprises a waveguide structure including a waveguide core. The structure further comprises a silicide layer, a first dielectric layer arranged in a lateral direction between the silicide layer and the waveguide core, and a second dielectric layer positioned over the waveguide core, the silicide layer, and the first dielectric layer. The first dielectric layer comprises a first material having a first thermal conductivity, and the second dielectric layer comprises a second material having a second thermal conductivity that is less than the first thermal conductivity.

Thermo-optic phase shifters

The disclosed subject matter relates to semiconductor devices for use in optoelectronic/photonic applications and integrated circuit (IC) chips. More particularly, the present disclosure relates to photonic devices having thermally conductive layers for the removal of heat from optoelectronic components in the photonic devices.

Photonic devices integrated with thermally conductive layers

Structures for an array of non-volatile memory cells and methods of forming a structure for an array of non-volatile memory cells. An active region of a substrate includes a first section having a side edge and a second section extending laterally from the side edge. The first section of the active region has a first length dimension in a direction parallel to the first side edge. The second section has a second length dimension in the direction parallel to the first side edge. The second length dimension is less than the first length dimension. A fin is positioned on the substrate in the second section of the active region. A gate structure extends over the fin and the second section of the active region.

Non-volatile memory cell arrays with a sectioned active region and methods of manufacturing thereof

Growing community of inventors

Halfmoon, NY, United States of America

Oscar Restrepo