International Business Machines Corporation

Ncipher Corporation Limited

Adaptec, Inc.

Nciper Corporation Limited

Oscar R Mitchell

Rajat Datta

William R Hardell, Jr

Gregory F Grohoski

Kyle Stein

James D Henson, Jr

Paul Joseph Jordan

Leslie Zsohar

Daniel B Reents

Robert Bradford Cohen

Daniel J Moore

Randall Findley

Greg North

Richard Goble

George Robert Blakley

James Garrett

Yongjae Rim

Tung M Nguyen

Rick Hall

Eric Thomas Shalkey

Eleanor Coy

Gary Alan Hoffman

Tung Manh Nguyen

Yonjae Rim

George Robert Blakely

An information-processing method for application-specific processing of messages. A message is received. Whether the message is in a selected application format is ascertained. If not, the message is routed to a next location. If so, the message is routed to a selected application processor, processed by the processor, and routed to the next location.

Application-specific information-processing method, system, and apparatus

A method, system, and device for encrypted packet inspection allowing an authorized third party device to monitor cryptographic handshaking information (full- duplex) between two other devices and together with the secret private key then transparently decrypt the bulk encrypted data stream. The scope of this invention encompasses many applications, three examples of which are firewalls, load balancers, and local network caches. Additionally, this invention achieves and contributes to the efficient handling of encrypted information in other ways, three examples of which are making switching, routing, and security decisions.

Encrypted packet inspection

A data encryption method performed with ring arithmetic operations using a residue number multiplication process wherein a first conversion to a first basis is done using a mixed radix system and a second conversion to a second basis is done using a mixed radix system. In some embodiments, a modulus C is be chosen of the form 2&#x2212;L, wherein C is a w-bit number and L is a low Hamming weight odd integer less than 2. And in some of those embodiments, the residue mod C is calculated via several steps. P is split into 2 w-bit words Hand L. Sis calculated as equal to L+(H2)+(H2)+ . . . +(H2)+H. Sis split into two w-bit words Hand L. Sis computed as being equal to L+(H2)+(H2)+ . . . +(H2)+H. Sis computed as being equal to S+(2+ . . . +2+1). And the residue is determined by comparing Sto 2. If S&#x3c;2, then the residue equals S. If S&#x2267;2, then the residue equals S&#x2212;2.

Ring arithmetic method, system, and apparatus

A data encryption method performed with ring arithmetic operations wherein a modulus C is be chosen of the form 2&#x2212;L, wherein C is a w-bit number and L is a low Hamming weight odd integer less than 2. And in some of those embodiments, the residue mod C is calculated via several steps. P is split into 2 w-bit words Hand L. Sis calculated as equal to L+(H2)+(H2)+ . . . +(H2)+H. Sis split into two w-bit words Hand L. Sis computed as being equal to L+(H2)+(H2)+ . . . +(H2)+H. Sis computed as being equal to S+(2+ . . . +2+1). And the residue is determined by comparing Sto 2. If S&#x3c;2, then the residue equals S. If S&#x2267;2, then the residue equals S&#x2212;2.

This invention relates to a system and method for adapting the ports of computing elements in transferring data between computing elements on a network. Ports of the computing elements are interconnected for data transfer through a switch complex. The interconnected ports are adapted to cooperate together in transferring the data. Data which is ordinarily designated to be transferred through one port of a computing element may be transferred through a different port.

System and method for controlling the direction of data flow between

A system and method for creating a high-level application programming interface allows simplified control and usage of digital data being transported over an IEEE 1394 serial bus under a variety of operational environments. The system and method of controlling communications on a communications bus includes determining a number of adapters attached to the communications bus, establishing a link between an application program and one or more of the adapters; allocating buffers for data transfer; mapping a memory buffer to a space in storage associated with the communications bus; and executing the applications program.

Method and apparatus for implementing an application programming

A computer networking system includes a cross bar switch and a protocol for operating the same. The crossbar switch typically connects a plurality of ports one to another and the protocol establishes a connection between a first desired port and a second desired port selected from the plurality of ports. Each port further connects to a compute element via a master bidirectional bus and a slave bidirectional bus. Any of the compute elements can serve as either a master or slave to any other compute element connected to the crossbar switch. A master port connects the bidirectional bus to the crossbar switch and a slave port connects the slave bidirectional bus to the crossbar switch. The master port is reserved for compute element initiated operations while the slave port is reserved for network initiated operations. The crossbar switch receives and transmits control, address, and data information over a CPU bus to a network router unit, which is used as the interface between the CPU and the crossbar switch to translate CPU bus protocol to switch protocol. The crossbar switch uses an in band switch design, which excludes explicit control pins to control the switch and relies on control being transmitted over wires shared between the data and the address functions. The switch and protocol support load, store, broadcast, compare, and swap and barrier synchronization primitives, using no control pins and minimizing overhead.

Crossbar switch apparatus and protocol

An architecture and method for booting a multi-processor system having processor local memory and shared global memory, with shared global memory access managed by an atomic memory access controller and cache coherence managed by software. Reset circuits are used to synchronize to a master clock a commonly distributed start signal and processor individualized restart sequences, which reset circuit signals are distributed to reset both local and global memory. Global memory testing is assigned to a processor based upon its rate status in completing an internal test sequence. The systems and methods are particularly suited to booting a group of multiple but relatively independent processors. Furthermore, the practice of the invention facilitates booting of such system when one or more of the processors have been disconnected or failed.

Apparatus and method for booting a multiple processor system having a

A system and method for managing spare bit steering information in a multi-processor system having a global/local memory architecture. During the system boot cycle one of the multiple processors is selected to test global memory and to configure the steering of the spare bits by bank or the like. Each processor tests its own local memory and defines the associated spare bit steering for the local memory. The global memory spare bit steering configuration information, as well as other global memory configuration information, in the selected processor is distributed to the other processors using registers in a commonly accessible atomic semaphore controller or through a commonly accessible block of global memory. Preferably, the selection of the processor to test the global memory is performed so that no single processor always has the responsibility. In this way, the acquisition of global memory spare bit steering information is not linked to the operative status of any one processor.

Apparatus and method for steering spare bit in a multiple processor

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Pflugerville, TX, United States of America

Oscar R Mitchell