Marvell International Limited

Lsi Logic Corporation

Synopsys, Inc.

Marvellworld Trade Ltd.

Oscar M Siguenza

Vinay Chitturi

Pantas Sutardja

Deepak Dattatraya Sherlekar

Stefan Graef

Duane G Breid

Bin Jiang

Gene Sluss

Hsien-Chih Chao

Mike Colwell

Devang Trivedi

Aspects of the disclosure provide a circuit. The circuit includes a switch and a switch controller. The switch is between a first node that receives a first power supply and a second node, and is controlled to couple/decouple the second node with the first node to switch on/off a second power supply at the second node. The switch controller is configured to generate a switch control signal to control a charging current flowing through the switch to switch on the second power supply.

Method and apparatus for power switching

In one or more embodiments, an integrated circuit includes a programmable memory, a key generation module and a module. The programmable memory is to maintain a first key portion. The key generation module is to generate a key using the first key portion from the programmable memory and a second key portion received via a memory interface. The module is to encrypt or decrypt data using the key.

Ser tolerant flip flop having a redundant latch

A circuit configured to resist a radiation strike includes a latch having an input node and an output node, and a first resistive element configured to be coupled to the first input node to resist a change of a state data at the input node from a radiation strike. The circuit further includes an input stage coupled to the input node and configured to be clocked to transfer the state data to the latch. The circuit further includes a pass circuit configured to be clocked after the input stage to couple the first resistive element to the input node after the input stage transfers the state data to the latch.

Various methods and apparatuses are described for a power distribution structure. In an embodiment, an integrated circuit contains power gating cells that each contain Metal Oxide Semiconductor (MOS) device switches located relative in the power distribution structure to power up and down a block of logic containing a plurality of individual cells using these MOS device switches. The MOS device switches can be tuned to requirements of a target block of logic in order to meet its optimal voltage drop requirements during its active operational state while minimizing leakage current in its off state.

Structures and methods for optimizing power consumption in an integrated chip design

A low impact buffer structure disposed in unused silicon area in a signal line routing channel between logic cell rows of an integrated circuit. In a buffer cell according to the invention, power to the buffer is provided by the power supply rails of one or more nearby logic cell rows. Both the connections to the supply rails and the connections between the transistors of the buffer cell are constructed of a polysilicon material and/or lower metal layer. In this manner, the buffer cell does not significantly impact the routing of metal signal lines in the signal line routing channel. In addition, the buffer cells can be arranged in a &ldquo;staggered&rdquo; configuration wherein separate buffers are provided in individual routing tracks of a signal line routing channel, further reducing the possibility of interference with normal signal routing. In addition, layout and routing tools according to the present invention are capable of monitoring the routing or loading of a signal line to determine when it reaches a length or load factor that may give rise to timing problems. When such a signal line is identified, the routing tool routes the signal line to the nearest available buffer cell or causes a buffer cell to be placed in a convenient location, preferably in the current routing channel. Following the routing process, updated netlist and timing information is generated for back-annotation to other design tools.

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San Jose, CA, United States of America

Oscar M Siguenza