International Business Machines Corporation

Oscar Conrad Strohacker

Stephen Gerard Shuma

Mark Steven Styduhar

Paul Steven Zuchowski

Kenneth Joseph Goodnow

Douglas Wayne Kemerer

Peter Albert Twombly

Douglas Willard Stout

Corey Kenneth Barrows

Andrew S Wienick

Glen Alan Jaquette

David Jones Craft

Francis A Kampf

Peter A Twembly

Paul S Zuchewski

Disclosed is a design structure for an associated first system for extending product life of a second system in the presence of phenomena that cause the exhibition of both performance degradation and recovery properties within system devices. The first system includes duplicate devices incorporated into the second system (e.g., on a shared bus). These duplicate devices are adapted to independently perform the same function within that second system. Reference signal generators, a reference signal comparator, a power controller and a state machine, working in combination, can be adapted to seamlessly switch performance of that same function within the second system between the duplicate devices based on a measurement of performance degradation to allow for device recovery. A predetermined policy accessible by the state machine dictates when and whether or not to initiate a switch.

Structure for system for extending the useful life of another system

The embodiments of the invention provide a design structure for detection and compensation of negative bias temperature instability (NBTI) induced threshold degradation. A semiconductor device is provided comprising at least one stress device having a voltage applied to its gate node and at least one reference device having a zero gate-to-source voltage. A controller is also provided to configure node voltages of the device and/or the reference device to reflect different regions of device operations found in digital and analog circuit applications. Moreover, the controller measures a difference in current between the stress device and the reference device to determine whether NBTI induced threshold degradation has occurred in the stress device. The controller also adjusts an output power supply voltage of the stress device until a performance of the stress device matches a performance of the reference device to account for the NBTI induced threshold degradation.

Mechanism for detection and compensation of NBTI induced threshold degradation

Disclosed are embodiments of a method and an associated first system for extending product life of a second system in the presence of phenomena that cause the exhibition of both performance degradation and recovery properties within system devices. The first system includes duplicate devices incorporated into the second system (e.g., on a shared bus). These duplicate devices are adapted to independently perform the same function within that second system. Reference signal generators, a reference signal comparator, a power controller and a state machine, working in combination, can be adapted to seamlessly switch performance of that same function within the second system between the duplicate devices based on a measurement of performance degradation to allow for device recovery. A predetermined policy accessible by the state machine dictates when and whether or not to initiate a switch.

Method and system for extending the useful life of another system

A design structure. The design structure includes: a first set of FETs having a designed first Vt and a second set of FETs having a designed second Vt, the first Vt different from the second Vt; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit configured to generate a compare signal based on a performance measurement of the first monitor circuit and of the second monitor circuit; a control unit responsive to the compare signal and configured to generate a control signal regulator based on the compare signal; and an adjustable voltage regulator responsive to the control signal and configured to voltage bias wells of FETs of the second set of FETs, the value of the voltage bias applied based on the control signal.

Methods and circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications

A circuit and a method for adjusting the performance of an integrated circuit, the method includes: comprising: (a) measuring the performance of a first monitor circuit having at least one field effect transistor (FET) of a first set of FETs, each FET of the first set of FETs having a designed first threshold voltage; (b) measuring the performance of a second monitor circuit having at least one field effect transistor (FET) of a second set of FETs, each FET of the second set of FETs having a designed second threshold voltage, the second threshold voltage different from the first threshold voltage; and (c) applying a bias voltage to wells of the FETs of the second set of FETs based on comparing a measured performance of the first and second monitor circuits to specified performances of the first and second monitor circuits.

Methods to reduce threshold voltage tolerance and skew in multi-threshold voltage applications

The embodiments of the invention provide an apparatus and method for detection and compensation of negative bias temperature instability (NBTI) induced threshold degradation. A semiconductor device is provided comprising at least one stress device having a voltage applied to its gate node and at least one reference device having a zero gate-to-source voltage. A controller is also provided to configure node voltages of the device and/or the reference device to reflect different regions of device operations found in digital and analog circuit applications. Moreover, the controller measures a difference in current between the stress device and the reference device to determine whether NBTI induced threshold degradation has occurred in the stress device. The controller also adjusts an output power supply voltage of the stress device until a performance of the stress device matches a performance of the reference device to account for the NBTI induced threshold degradation.

A circuit and a method for adjusting the performance of an integrated circuit, the circuit includes: first and second sets of FETs having respective first and second threshold voltages, the first threshold voltage different from the second threshold voltage; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit adapted to generate a compare signal based on a performance measurement of the first monitor circuit and a performance measurement of the second monitor circuit; and a control unit adapted to generate a control signal to a voltage regulator based on the compare signal, the voltage regulator adapted to supply a bias voltage to wells of FETs of the second set of FETs, the value of the bias voltage based on the control signal.

Circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications

A preprocessor for processing sample data, particularly digital video data, to improve lossless sliding window type Lempel-Ziv compression of the data. Sliding window Lempel-Ziv compression is improved by transposing the multiple bit per pixel data samples before compression so that the relatively repetitive higher order bits of successive pixels are compressed separately from the relatively volatile lower order bits of the successive pixels. The transposition is particularly suited for bit plane configured frame buffers in that compression and decompression grouping is readily performed by the manipulation of data within the individual bit planes.

Preprocessing multiple bit per pixel sampled data for Lempel-Ziv compression

A method of reducing data expansion during data compression is provided that allows the coding scheme used to compress data to be swapped between two or more coding schemes. Specifically, a coding window is provided that allows analysis of the compression potential of data within the coding window. The data within the coding window then is analyzed to determine the compression potential of the data. If the compression potential of the data exceeds a first predetermined value, the coding scheme used to compress the data within the coding window is swapped from one coding scheme to another. Preferably the first predetermined value is programmable and is related to the bit cost required to swap back and forth between coding schemes. The two preferred coding schemes are ALDC Lempel-Ziv 1 coding and a pass-through coding scheme wherein raw data is passed unencoded.

Method for reducing data expansion during data compression

In a data processing system, a block of N bytes is selected, wherein N is greater than one. Thereafter, a group of N data cells is created wherein each cell has a physical tag for indicating a physical order in the group and a substring that includes a sequence of bytes from the block of N bytes. Next, the group of N cells is sorted lexically to establish a lexical order based upon the lexical value of the substring in each of the N cells. Matching strings in the substrings of selected ones of the N cells are identified in the lexically sorted group of N cells. Thereafter, the block of N bytes is encoded utilizing the identified matching strings to produce a compressed data set, wherein the compressed data set is efficiently produced by identifying redundant information in the lexically sorted group of N cells. Such encoding may be accomplished by comparing lexically adjacent cells in the lexically sorted group of N cells to identify matching strings.

Method and system in a data processing system for efficiently

Systems and methods for compressing data. Lempel-Ziv data compression is applied in the context of an exhaustive sliding window implementation using a large character history bit pattern memory. Shifted updating of the character history bit pattern memory is accomplished through a pointer system. Linear patterns of bits, derived by COPY function from the character history bit pattern memory or by bit wise AND logic combination of selected bit patterns, are circularly shifted in synchronism with new data characters using a toroidal bit shift register. The relatively long bit strings subject to shifting are converted to a matrix format, shifted with fewer affected bits and returned to a linear format. The systems and methods materially improve the speed of exhaustive sliding window data compression as accomplished by general purpose processors.

Sliding window data compression using a toroidal bit shift register

An apparatus for compressing data including apparatus for using a received data element as an address to a location in a memory, an apparatus for determining whether the addressed memory location contains a first record of a first matching data element, and an apparatus for generating a pointer to the first matching data element. In addition, a method for compressing data including the steps of using a received data element as an address to a location in a memory, determining whether the addressed memory location contains a first record of a first matching data element, and generating a pointer to the first matching data element.

Method and apparatus for compressing data

A method and system in a data processing system for efficiently rotating a linear bit pattern, wherein the data processing system includes a register for efficiently performing a rotate operation on a portion of the linear bit pattern, where such a portion has a selected number of bits. The linear bit pattern is divided into a plurality of pattern groups, where each of such pattern groups has a number of bits equal to a group length. Thereafter, a matrix of bits is formed. Such a matrix has groups of bits along a plurality of rows and columns, wherein each row contains a number of bits equal to a shift operand length, and each column contains a number of bits equal to the group length. Bits in a selected row are rotated. Thereafter, each row, as a group of bits, is rotated such that bits in each column remain in the same column. After manipulating the matrix, the contents of the matrix represents the linear bit pattern rotated by one bit.

Growing community of inventors

Leander, TX, United States of America

Oscar Conrad Strohacker