Hitachi, Ltd.

Hitachi Denshi Kabushiki Kaisha

Osamu Yumoto

Yasuhiro Kita

Masahito Kobayashi

Yoshimune Hagiwara

Takashi Akazawa

Yuzo Kita

Narimichi Maeda

Shizuo Sugiyama

Yoshitaka Takasaki

Toshiro Suzuki

Michio Suzuki

Tadao Kaji

Kohei Ishizuka

Hiroshi Takatori

Yoshinori Nagoya

Jun'ichi Nakagawa

Teruhisa Azumaguchi

Akisada Moriguchi

Hironori Saito

Masaharu Hata

A constant-voltage power source circuit includes a first current mirror circuit having a diode and a first transistor and a second current mirror circuit having at least second and third transistors, which sets a current flowing to the first current mirror circuit to be substantially equal to a current flowing to the second mirror circuit, and provides the current flowing to the second current mirror circuit to a fourth transistor that determines an output voltage. With this arrangement, a current flowing to the current mirror circuits structured by the diode and transistors is determined by a forward characteristic of the diode, and this current becomes a constant current which is hardly affected by a variation of a power source voltage. When this current flows to the two current mirror circuits including transistors and then flows to the transistor which determines an output voltage, it is possible to hold a voltage between the base and the emitter of the transistor which determines an output voltage, at substantially a constant value without being affected by a variation of the power source voltage.

Low-constant voltage supply circuit

A signal processor having a wide dynamic range and which can process both data in the fixed point representation and data in the floating point representation by the use of a single floating-point arithmetic circuit is capable of processing digital signals, such as voice signals, at high speed and in real time. In addition, this signal processor includes an arithmetic logic unit for floating point data and/or fixed point data in which there is selectively provided a first pair of first and second floating point data which are to be subjected to an arithmetic operation, or a second pair of data consisting of third floating (fixed) point data which is to be converted to fixed (floating) point data and fourth floating point data which is a reference data for the conversion. If the first pair is selected the first and second pair of floating point data are subjected to the arithmetic operation. If the second pair is selected, the conversion of the fixed (floating) point data to floating (fixed) point data is effected by normalizing the third data with the value of the exponent part of the fourth data.

Arithmetic logic unit for floating point data and/or fixed point data

In an adder for floating point data, two floating point data are adjusted so that the exponent parts have the same value and the resulting adjusted mantissa parts are added. A first shift signal is generated on the basis of the result of the added mantissa parts and having a value necessary for normalization of the addition result, and a second shift signal is generated having a value equal to the difference between the adjusted exponent part of the floating point data and a minimum value predetermined for an exponent of any floating point data at which underflow occurs. The result of addition of the adjusted mantissa parts is shifted on the basis of said second shift signal or said first shift signal depending on whether or not an underflow occurs.

Adder for floating point data suitable for digital signal processing

A signal processor having a wide dynamic range and which can process both data in the fixed point representation and data in the floating point representation by the use of a single floating-point arithmetic circuit is capable of processing digital signals, such as voice signals, at high speed and in real time. In addition, this signal processor is capable of executing data input/output operations with an external circuit in the data format of the fixed point representation and of performing internal operations in the floating point representation format. Further, conversion of an operational result from fixed point representation to floating point representation, and vice versa, can be performed internally in accordance with program instruction.

Digital processor with floating point multiplier and adder suitable for

A small-sized LSI variable equalizer is provided for accurately equalizing waveforms of signals transmitted via transmission lines of different distances. Variable equalizer units capable of stepwise changing the equalizing characteristics thereof are connected in series with each other with the variable equalizer units having variable step widths different from each other. An output signal of the variable equalizer units is compared with a reference signal to convert the comparison output signal to a digital signal which includes an upper order bits and lower order bits, whereby one of the equalizer units which has a wide variable step width is controlled by the upper order bits and the other of the equalizer units which has a narrow variable step width is controlled by the lower order bits.

Variable equalizer

In order to realize a precision variable equalizer of little errors by a simple circuit arrangement, a plurality of variable transmission circuits having variable transfer coefficients are connected in series between input and output terminals, and feed-back and feed-forward are applied from input and output sides of the respective variable transmission circuits to input and output portions of the variable equalizer through transmission networks having specified transfer characteristics.

In a method of manufacturing a semiconductor device, wherein an element forming a region of one conductivity type isolated by an oxide layer is disposed on a semiconductor substrate of the opposite conductivity type, a ring-shaped high impurity concentration region of the opposite conductivity type is formed on a portion of the semiconductor substrate so as to surround the isolated region to thereby prevent the formation of a parasitic channel and to stabilize the surface potential of the substrate.

Method of manufacturing semiconductor device having oxide isolation

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Kokubunji, Japan

Osamu Yumoto