Hitachi Cable, Inc.

Osamu Yoshioka

Takaharu Yonemoto

Hiroshi Sugimoto

Noriaki Taketani

Shigeo Hagiya

Gen Murakami

Tatsuya Ohtaka

Kazuhisa Hatano

A lead frame for LOC to which a semiconductor chip is fixed within a semiconductor chip-mounting region. In addition to applying insulative adhesives to the conventional portions or spots which are on the bottom surfaces of the leading edges of respective inner leads for wire bonding to the pads for the semiconductor ship, the insulative adhesives are applied to other portions of the inner leads in the vicinity of the semiconductor chip-mounting region. Accordingly, the area for bonding the semiconductor chip can be enlarged resulting in improvements in the stability of adhesion between the leads and the semiconductor chip, and in the stabilities of wire bonding and resin molding.

Lead frame for lead on chip

A lead frame is provided which enables a coating of an insulating adhesive for fixing a semiconductor chip to be evenly and thickly foamed on inner leads. In a lead frame wherein an insulating adhesive for fixing a semiconductor chip is applied to a semiconductor chip mounting region, inner leads,are set to a value of w/s of not more than 1 wherein w represents the lead width and s represents the lead spacing.

Lead frame

A lead frame for LOC is provided which can reduce a variation in coverage of an insulating adhesive, permitting the fixation of a semiconductor chip and wire bonding to be stably performed. In a lead frame for LOC 10 wherein an insulating adhesive for fixing a semiconductor chip is applied to inner leads 11 in their semiconductor chip mounting region, a coverage regulating lead 14 is provided outside the semiconductor chip mounting region and adjacent to inner leads 11a, 11b located at the end of the semiconductor chip mounting region, permitting the insulting adhesive to be homogeneously applied to each of the inner leads 11 without creating any variation in coverage of the adhesive.

Lead frame for LOC having a regulating lead to prevent variation in

A semiconductor device has a semi-conductor chip 1 having bonding pads 2 thereon, conductive leads 4, each of which comprises an inner lead 41 and an outer lead 42, insulating adhesive tapes 3 by which each of the inner leads 41 of the leads 4 is stuck to the surface 1a of the semiconductor chip 1, bonding wires 6 by which each of the leads 4 is electrically connected to each corresponding bonding pad 2. The semiconductor chip 1, bonding pad 2, adhesive tapes 3, inner leads 41, and bonding wires 6 are molded by a molding resin 5. The boundary of the inner lead 41 and the cuter lead 42 of the lead 4 is bent in S-shape so that there is a step between inner lead 41 and the upper side portion 42a of the outer lead 42 in a certain depth. Then the outer lead 42 protrude out of the molding resin and extend in J-shape. The surface 4a of the upper side portion 42a of the outer lead 42 is higher than the top of the looped bonding wire 6.

Semiconductor device having lead on chip structure

A lead frame for LOC is provided which, even when an adhesive is applied to a lead prepared by stamping, can ensure insulation of a semiconductor element mounted from the lead. In applying an adhesive to a predetermined position of an inner lead 1 in a lead frame prepared by stamping to form an adhesive layer 4, the adhesive layer 4 is provided on the droop face of the inner lead 1. The droop face has no burr and a bulged center portion, permitting contact, derived from the burr, between a lead face and a semiconductor element, to be avoided, which ensures satisfactory insulation of the semiconductor element mounted from the lead.

Growing community of inventors

Ibaraki, Japan

Osamu Yoshioka