Hitachi, Ltd.

Osamu Yamashiro

Kanji Yoh

Satoshi Meguro

Shunji Shimada

Yoshikazu Hatsukano

Isamu Kobayashi

Naoki Yashiki

Koichi Nagasawa

Kotaro Nishimura

Masato Iwabuchi

Goichi Yokomizo

Harumi Wakimoto

Takeshi Gappa

Kazutaka Narita

Mikako Miyama

Tadashi Funakubo

Toyohiko Hongo

Munehiro Ogawa, Deceased

Hitoshi Sugihara

Masami Kinoshita

Saburo Hojo

A mixed mode simulation method and apparatus are provided for highly accurately simulating the total characteristics of a digital analyzed circuit portion and an analog analyzed circuit portion, which are both subjected to mixed mode simulation, in consideration of the influence exerted on the analog analyzed circuit portion by a current consumed by the digital analyzed circuit portion. More particularly, a current value of an equivalent circuit for current calculation modeled for providing the analog analyzed circuit portion with a current generated due to an operating state of the digital analyzed circuit portion realized by logic simulation is determined in synchronism with the logic simulation, and the equivalent circuit for current calculation derived thereby is composed with the analog analyzed circuit portion, and this composite circuit is subjected to circuit simulation.

Mixed mode simulation method and simulator

This reference voltage generator device detects a voltage corresponding to an energy gap of a semiconductor, or a voltage of a value close thereto, or a voltage based on an energy level of a semiconductor, and generates the detected voltage as a reference voltage. The reference voltage is generated by detecting a difference of threshold voltages of first and second insulated gate field-effect transistors (IGFETs). Gate electrodes of the first and second IGFETs are formed on gate insulating films which are formed on different surface areas of an identical semiconductor substrate under substantially the same conditions. The gate electrodes of the first and second IGFETs are respectively made of two semiconductors which are selected from among a semiconductor of a first conductivity type, a semiconductor of a second conductivity type and an intrinsic semiconductor made of an identical semiconductor material, and which have Fermi energy levels of values different from each other. The channels of the first and second IGFETs have an identical conductivity type. On the basis of a self-alignment structure, at least those parts of first and second polycrystalline semiconductor regions being the gate electrodes of the first and second IGFETs which are proximate to source and drain regions are doped with the same impurity as that of the source and drain regions, and a central part of one of the first and second polycrystalline semiconductor regions is doped with an impurity of a selected one of the first conductivity type and the second conductivity type.

Reference voltage generator device

A method is provided for manufacturing a reference voltage generator device which detects a voltage corresponding to an energy gap of a semiconductor, or a voltage of a value close thereto, or a voltage based on an energy level of a semiconductor, and generates the detected voltage as a reference voltage. The reference voltage is generated by detecting a difference of threshold voltages of first and second insulated gate field-effect transistors (IGFETs). Gate electrodes of the first and second IGFETs are formed on gate insulating films which are formed on different surface areas of an identical semiconductor substrate under substantially the same conditions. The gate electrodes of the first and second IGFETs are respectively made of two semiconductors which are selected from among a semiconductor of a first conductivity type, a semiconductor of a second conductivity type and an intrinsic semiconductor made of an identical semiconductor material, but which have Fermi energy levels of values different from each other.

Method of manufacturing a reference voltage generator device

A battery checker utilizes a reference voltage generator device which detects a voltage corresponding to an energy gap of a semiconductor, or a voltage of a value close thereto, or a voltage based on an energy level of a semiconductor, and generates the detected voltage as a reference voltage. The reference voltage is generated by detecting a difference of threshold voltages of first and second insulated gate field-effect transistors (IGFETs). Gate electrodes of the first and second IGFETs are formed on gate insulating films which are formed on different surface areas of an identical semiconductor substrate under substantially the same conditions. The gate electrodes of the first and second IGFETs are respectively made of two semiconductors which are selected from among a semiconductor of a first conductivity type, a semiconductor of a second conductivity type and an intrinsic semiconductor made of an identical semiconductor material, but which have Fermi energy levels of values different from each other.

Battery checker

According to the present invention, the voltage of a battery is supplied to an electronic circuit such as a watch circuit through a step down circuit which is constructed of capacitors and switching MIDFETs. The step down circuit performs a current converting operation as well as a voltage converting operation. The operating current of the electronic circuit is reduced by the reduction in the operating voltage of the same. As a result that the operating current level of the electronic circuit is dropped and that the current conversion is performed by the step down circuit, the battery current is relatively largely dropped. The construction thus far described elongates the lifetime of the battery. According to the present invention, therefore, there is provided a circuit which is proper for driving the step down circuit.

Low power consumption electronic circuit

A voltage detection circuit adapted for use in an electronic timepiece in which a source voltage from a battery power source, etc. is voltage-divided and applied to an input of a logic circuit including complementary MIS FETs so as to compare the divided source voltage with a reference potential level and to detect whether the source voltage is above a predetermined value or not. In the logic circuit, the logic threshold is set in the neighborhood of the threshold voltage of one MIS FET to establish a reference potential level. Advantages are provided in integrating the circuit in a semiconductor integrated circuit such that parameters relevant to the manufacturing processes do not influence the reference potential level very much and the dispersion in the detected voltage due to the fluctuations in the manufacturing processes are minimized.

Voltage detection circuit

A complementary amplifier circuit includes a p-channel MISFET and an n-channel MIS connected in series. The gate of the p-channel FET transistor is D.C. biased by a high impedance resistor connected between the gate and drain electrodes, and the gate of the n-channel FET is D.C. biased by a current mirror circuit formed by another n-channel FET. This complementary amplifier circuit has the advantages that the operational lower limit voltage thereof is equal to the threshold voltage of one of the MOSFETs and that stabilized operation of the amplifier is easily obtained.

Complementary amplifier circuit

A semiconductor integrated amplifier having a p-channel type MISFET and an n-channel type MISFET which are integrated in a single semiconductor substrate, a load resistance connected between the drain regions of the MISFETs, a power source to which the MISFETs are connected in series, and a DC current blocking capacitor through which the gates of the MISFETs are connected to each other. The amplifier has a gate capacitance one terminal of which is constituted by a well formed in the substrate and connected to high voltage side of power supply, while the other electrode thereof is constituted by a gate electrode formed on the well and connected to the low voltage side of the power supply. Parasitic capacitance of the capacitor is considerably reduced to allow a wider range of frequency adjustment of the amplifier.

Semiconductor integrated amplifier

In oscillators such as those used in electronic watches, low power consumption is quite desirable. To accomplish this, an oscillator is provided including a complementary inverter amplifier circuit comprising a complementary inverter including a p-channel MIS FET connected to a first source potential, an n-channel MIS FET connected to a second source potential, and the gate of the two FETs being applied with a common linear input. Respective load resistors are connected to the drains of the complementary FETs, an output being derived from the interconnection point of the load resistors or from the drains of the FETs. Further, a bias resistor is connected between the gate and the drain of each of the complementary FETs, the input being supplied to the gates of the FETs through respective capacitors. The p-channel FET and n-channel FET are individually biased so that the circuit may serve as a class B push pull amplifier of low power consumption.

Crystal oscillator using a class B complementary MIS amplifier

A complementary inverter amplifier circuit comprising a complementary inverter including a p-channel MIS FET connected to a first source potential, an n-channel MIS FET connected to a second source potential, the gate of the two FETs being applied with a common linear input, respective load resistors connected to the drains of the complementary FETs, an output being derived from the interconnection point of the load resistors or from the drains of the FETs, and a bias resistor connected between the gate and the drain of each of the complementary FETs, the input being supplied to the gates of the FETs through respective capacitors. The p-channel FET and n-channel FET are individually biased so that the circuit may serve as a class B push pull amplifier of low power consumption.

Class B FET amplifier circuit

In a crystal-controlled oscillator circuit comprising a complementary-MOS inverter provided with a crystal in the feed-back circuit, an initiation circuit is provided which comprises another complementary-MOS inverter connected in parallel to said MOS inverter only at the time of initiation. This oscillator circuit includes a parallel circuit connection of two complementary MOS inverters at the time of initiation and hence has a large driving power and a short oscillation initiation time. Because of rendering one complementary MOS inverter to be cut off at the time of normal oscillation, the power consumption is reduced.

Initiation circuit in a crystal-controlled oscillator

In an electronic circuit such as MIS oscillation or amplifier circuit in which a MISFET or MISFET's is used as an amplifying element and a bias resistor is provided between input and output sides, a divided voltage of a power voltage determined by capacitive elements provided at the input side is selected to be equal to a bias voltage determined by the bias resistor, thereby preventing influence due to the variation in power voltage.

Electronic circuit having a misfet as an amplifying element

A constant-current circuit has a depletion type FET and a series circuit consisting of an impedance element and an enhancement type FET connected in parallel between two terminals. The gate electrodes of the respective FET's are connected to a juncture between the impedance element and the enhancement type FET, and current which flows through the depletion type FET is set to be sufficiently larger than a current which flows through the series circuit. The voltage across the enhancement type FET is made substantially equal to a threshold voltage thereof, whereby the constant current characteristics of such constant-current circuits are checked from being dispersed.

Constant-current circuit

This specification discloses an improvement for a voltage booster circuit. The improvement lies mainly in the use of MISFETs as switching means in a level converting circuit constructed in a complementary MIS semiconductor integrated circuit and therefore the voltage loss due to the conventional switching means can be prevented.

Voltage booster circuit using level shifter composed of two

A constant-current circuit comprising a first enhancement type FET, a depletion type FET having its drain and source connected to the drain and gate of the first enhancement type FET respectively, a second enhancement type FET having its drain and source connected to the gate and source of the first enhancement type FET and a series connection of two impedance elements having its ends connected to the source of the depletion type FET and to the source of the second enhancement type FET, the juncture between the two impedance elements being connected to the gate of the second enhancement type FET, whereby the constant-current characteristics of such constant-current circuits are checked from being dispersed.

Growing community of inventors

Ohmiya, Japan

Osamu Yamashiro