Kabushiki Kaisha Toshiba

Kioxia Corporation

Toshiba Memory Corporation

Osamu Yamane

Shinji Saito

Kei Kaneko

Tadashi Iguchi

Rei Hashimoto

Tsutomu Kakuno

Akira Tsumura

Kazuyuki Masukawa

Yoshihiro Yanai

Miki Toshima

Takeshi Fujiwara

Hiromitsu Mashita

Yoshihiro Uozumi

Yosuke Okamoto

Yasunobu Kai

Seiichi Omoto

Youyang Ng

Takuji Ohashi

Bo Wang

An information processing apparatus has an acquisitor configured to acquire an entire area image obtained by capturing an entire area of a processing surface of a wafer including at least one defect, a training image selector configured to select, as a training image, a partial image including at least one defect from the entire area image, a model constructor configured to construct a calculation model of generating a label image obtained by extracting and binarizing the defect included in the partial image, and a learner configured to update a parameter of the calculation model based on a difference between the label image generated by inputting the training image to the calculation model and a reference label image obtained by extracting and binarizing the defect of the training image.

Information processing apparatus and information processing method

An alignment apparatus according to one embodiment, includes: a first and a second stage; a first and a second detector; a first and a second moving mechanism; and a controller. The first and second stages are configured to respectively hold a first and a second semiconductor substrate on which a first and a second alignment mark are respectively disposed. The first and second moving mechanisms are configured to respectively move the first and second stages relatively to each other. The controller is configured to perform the following (a), (b). (a) The controller control the detectors and the moving mechanisms to cause the first detector to detect the second alignment mark and to cause the second detector to detect the first alignment mark. (b) The controller calculate a position deviation between the substrates in accordance with results of the detections.

Alignment apparatus and method of manufacturing semiconductor device

A distributed feedback semiconductor laser of includes a semiconductor stacked body and a first electrode. The semiconductor stacked body includes a first layer, an active layer that is provided on the first layer and is configured to emit laser light by an intersubband optical transition, and a second layer that is provided on the active layer. The semiconductor stacked body has a first surface including a flat portion and a trench portion; the flat portion includes a front surface of the second layer; the trench portion reaches the first layer from the front surface; the flat portion includes a first region and a second region; the first region extends along a first straight line; the second region extends to be orthogonal to the first straight line; and the trench portion and the second region outside the first region form a diffraction grating having a prescribed pitch along the first straight line. The first electrode is provided in the first region.

Distributed feedback semiconductor laser

According to one embodiment, in a position measuring method, alignment measurement in a light exposure process is executed by irradiating a first mark with light having a wavelength of &#x3bb;1, with respect to a processing object that includes a first layer and a second layer stacked above a substrate and a resist applied on the second layer. The first mark is provided in the first layer and includes a plurality of segments arranged at a pitch smaller than a resolution limit given by light having the wavelength of &#x3bb;1. Then, overlay measurement is executed by irradiating the first mark and a second mark with light having a wavelength of &#x3bb;2 shorter than the wavelength of &#x3bb;1. The second mark has been formed by performing a light exposure and development process to the resist, and includes a plurality of segments arranged at the pitch.

Position measuring method, position measuring apparatus, and semiconductor device manufacturing method

A terahertz quantum cascade laser device includes a substrate, q semiconductor stacked body and a first electrode. The semiconductor stacked body includes an active layer and a first clad layer. The active layer is provided on the substrate and is configured to emit infrared laser light by an intersubband optical transition. The first clad layer is provided on the active layer. A ridge waveguide is provided in the semiconductor stacked body. A first distributed feedback region and a second distributed feedback region are provided at an upper surface of the first clad layer to be separated from each other along an extension direction of the ridge waveguide. The first electrode is provided at the upper surface of the first clad layer. A planar size of the first distributed feedback region is smaller than a planar size of the second distributed feedback region.

Terahertz quantum cascade laser device

A surface emitting quantum cascade laser includes an active layer, a first semiconductor layer, and first electrode. The active layer has a plurality of quantum well layers stacked therein. The active layer is capable of emitting laser light by inter-subband transition. The first semiconductor layer is provided on the active layer and having a first surface provided with a plurality of pits so as to constitute a two-dimensional lattice. The first electrode is provided on the first semiconductor layer and having a periodic opening. Each pit is asymmetric with respect to a line parallel to a side of the lattice. The laser light is emitted in a direction generally perpendicular to the active layer from a pit exposed to the opening.

Surface emitting quantum cascade laser

According to one embodiment, a semiconductor memory device includes a semiconductor substrate and a memory array. The semiconductor substrate has a first face. The memory array region is provided on the first face and includes a plurality of semiconductor pillars. The semiconductor pillars extend in a first direction perpendicular to the first face. Each of the semiconductor pillars includes a plurality of memory cells connected in series. Each of the semiconductor pillars is disposed at the nodes of a honeycomb shape when viewed in the first direction. When the semiconductor pillars are projected onto a first plane along the first and second directions perpendicular to the first direction, a component in the second direction of an interval between the semiconductor pillars has first and second intervals repeated alternately. The second interval is an integer multiple of the first interval greater than or equal to 2.

Semiconductor memory device and method for manufacturing same

According to one embodiment, an exposure tolerance estimation method is disclosed. The method can include setting a plurality of regions along a first surface of a substrate. The method can form a plurality of patterns for estimation by performing exposure on each of the regions using at least three levels of exposure condition using an exposure mask. The method can measure dimensions of the patterns for estimation and find relationships between the exposure condition and the dimensions. The method can select a first region from the regions. In the first region, a first dimension of a first pattern for estimation formed by exposure using a first exposure condition of an intermediate level out of the at least three levels falls within a previously set range. In addition, the method can calculate an exposure tolerance from a relationship between the first exposure condition and the first dimension.

Exposure tolerance estimation method and method for manufacturing semiconductor device

According to one embodiment, a method for manufacturing a semiconductor device includes forming a stacked body on a substrate. The stacked body includes a plurality of first conductive layers including a metallic element as a main component and a plurality of second conductive layers including a metallic element as a main component provided respectively between the first conductive layers. The method includes making a hole to pierce the stacked body. The method includes making a slit to divide the stacked body. The method includes making a gap between the first conductive layers by removing the second conductive layers by etching via the slit or the hole. The method includes forming a memory film including a charge storage film at a side wall of the hole. The method includes forming a channel body on an inner side of the memory film inside the hole.

Growing community of inventors

Yokohama, Japan

Osamu Yamane