Fujitsu Corporation

Socionext Inc.

Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Osamu Uno

Masahiro Iwamoto

Kunihiro Itoh

Yuichi Itonaga

Hajime Ohmi

Tomohiko Koto

Toyoki Suzuki

Mitsuaki Tomida

Kenichi Konishi

An input circuit includes an input buffer circuit using a first node as an input and a second node as an output, an N-type transistor having a source coupled to the input terminal, a drain coupled to the first node, and a gate coupled to a power supply, and a pull-up circuit provided between the first node and the power supply. The pull-up circuit is configured to make the power supply and the first node conducive with each other for a predetermined period when the input signal transitions from low to high and not to make the power supply and the first node conductive with each other when the input signal transitions from high to low.

Input circuit

A semiconductor apparatus includes an internal circuit connected to a first power line to which a first power voltage is applied; a transistor including a first terminal, which is connected to a node to which an input voltage is applied, a second terminal connected to the internal circuit, and a control terminal to which a control voltage is applied; and a voltage control circuit, which is connected to the node, generating the control voltage. Further, the voltage control circuit includes a step-down circuit generating an internal voltage by lowering the input voltage applied to the node, and a switching circuit, which is connected to the first power line, generating the control voltage based on the first power voltage and the internal voltage.

Semiconductor apparatus

A level conversion circuit includes: first P-ch and N-ch transistors and second P-ch and N-ch transistors respectively connected in series between first and second power sources; third and fourth P-ch transistors respectively connected between the gates of the second and first P-ch transistors and the drain of the first and second P-ch transistors; and fifth and sixth P-ch transistors respectively connected between the gates of the second and first P-ch transistors and a third power source, wherein differential input signals are applied to the gates of the first and second N-ch transistors, a bias voltage is applied to the gates of the third and fourth P-ch transistors, the gate of the fifth and sixth P-ch transistors are respectively connected to connection nodes of the first P-ch and N-ch transistors the second P-ch and N-ch transistors.

Level converter circuit

An output buffer circuit includes first and second output circuits, and those output terminals are coupled to each other. The first output circuit outputs a first signal having a voltage level of a first high potential power supply or a low potential power supply and includes a first output transistor at a high potential side. The second output circuit outputs a second signal having a voltage level of a second high potential power supply, which is lower than the first high potential power supply, or the low potential power supply and includes a second output transistor at a high potential side. A control circuit sets the gate and back gate of at least one of the first and second output transistor to the voltage level of the second high potential power supply when the first high potential power supply is deactivated and the second high potential power supply is activated.

Output buffer circuit and input/output buffer circuit

An input/output circuit, operable in an input mode and an output mode, for receiving data and an enable signal, the input/output circuit including an input/output terminal; a pull-up output transistor including a gate; a first logic circuit including an output node coupled to the gate of the pull-up output transistor; a pull-down output transistor including a gate; a second logic circuit coupled to the gate of the pull-down output transistor, and the second logic circuit inactivating the pull-down output transistor in the input mode; and a gate signal generation unit configured to generate a gate signal for inactivating the pull-up output transistor in accordance with the enable signal and an input signal provided from an external device to the input/output terminal in the input mode.

Input/output circuit

An input/output circuit operable in input and output modes and including an input/output terminal, pull-up and pull-down output transistors, and first and second logic circuits operated in accordance with data and an enable signal. A control circuit maintains the pull-up output transistor in an inactivated state regardless of the voltage applied to the input/output terminal in the input mode. A switch circuit disconnects the first logic circuit from a power supply when an input signal having voltage higher than the power supply voltage of the power supply is input to the input/output terminal in the input mode. A back gate control circuit supplies back gates of P-channel MOS transistors in the first logic circuit and the switch circuit with back gate voltage having the same voltage as the input signal when the input signal is input in the input mode.

A tolerant input circuit that functions stably regardless of fabrication differences without having to adjust the threshold value of an input circuit. The tolerant input circuit includes a step-down device configured by an N-channel MOS transistor connected between an input pad and the input circuit. Voltage from a power supply is supplied to the gate of the N-channel MOS transistor in the step-down device to decrease the voltage of a high voltage signal provided to the input pad to the voltage of the power supply or lower. The signal with decreased voltage is provided to the input circuit. The tolerant input circuit includes a back gate voltage control circuit for increasing back gate voltage of the N-channel MOS transistor in the step-down device when the input pad is provided with a high voltage signal.

Tolerant input circuit

In a two-stage inverter circuit including an inverter circuit constituted by first and second FETs and an inverter circuit constituted by two FETs, a source and a gate of a third FET are connected to a first power source and a second power source, respectively. A drain of the third FET is connected to a source of the first FET. A source and a gate of a fourth FET are connected to the first power source and the second power source, respectively. A drain of the fourth FET is connected to a source of a seventh FET. A gate of the seventh FET is connected to the second power source, and a drain of the seventh FET is connected to a back gates of the first, third, fourth, seventh and fifth FETs. The drain of the third FET is connected to the drain of the fourth FET.

Buffer circuit and integrated circuit

In a semiconductor device in which an applying voltage higher than a power supply voltage VDD is inputted to a terminal BUS, when the voltage VBUS is less than a voltage of the power supply voltage VDD plus a threshold voltage Vthp, a voltage obtained by subtracting a threshold voltage Vthn from the power supply voltage VDD is applied to the gate terminal Gand the PMOS transistor Pbecomes conductive. The power supply voltage VDD is supplied to the gate terminal Gto turn the PMOS transistor Poff. When the voltage VBUS is equal to or higher than the voltage of the power supply voltage VDD plus the threshold voltage Vthp, the voltage VBUS is supplied to the gate terminal Gto turn the PMOS transistor Poff, and the PMOS transistor Pconducts and supplies the voltage VBUS to the gate terminal Gto turn the PMOS transistor Poff. The voltage level is correctly maintained without an undesirable leak current from the terminal BUS regardless of the applying voltage VBUS.

Semiconductor device

An output buffer includes a first drive circuit that receives an input signal having a sharp waveform and generates an output signal that has a gentle waveform. A second drive circuit is connected to the first drive circuit at an output terminal and has a lower impedance than the first drive circuit. A delay circuit is also connected to the output terminal and generates a delayed output signal. A first control circuit is connected between the delay circuit and the second drive circuit and receives the input signal and the delayed output signal and generates a first control signal used to drive the second drive circuit.

Output buffer circuit and control method therefor

In an input/output buffer circuit to which input signal voltage VBUS higher than power source voltage VDD is possibly inputted to an input/output terminal BUS, a gate terminal G is controlled by a signal in-phase to a input/output mode switching signal CNT outputted from a buffer circuit , and the power source voltage VDD is applied when it is an input mode. When the input signal voltage VBUS is lower than voltage obtained by applying threshold voltage Vthp of PMOS transistor to the power source voltage VDD (VBUS<VDD&plus;Vthp), voltage obtained by subtracting threshold voltage Vthn of NMOS transistor from the power source voltage VDD is applied to a gate terminal G (VG &equals;VDD&minus;Vthn). On condition that Vthn>Vthp, a PMOS transistor P gets conductive, whereby the power source voltage VDD is applied to a gate terminal G and PMOS transistor P is turned off. Thereby, an unnecessary current path is not formed. There is thus provided an input/output buffer circuit wherein unnecessary current does not flow in the input/output terminal BUS.

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Osamu Uno