Seiko Instruments Inc

Osamu Uehara

Kiyoshi Yoshikawa

Fumiyasu Utsunomiya

Jun Osanai

Michiyasu Deguchi

Toshiyuki Tsuzaki

Hiroyuki Masuko

Hiroki Wake

Provided is a voltage regulator which includes an inrush current prevention circuit so that no current is consumed after the start-up of the voltage regulator. A start-up circuit of the voltage regulator includes: a constant current circuit; a first transistor connected between the constant current circuit and a constant voltage generation circuit; a second transistor including a drain connected to a gate of the first transistor, and a gate to which a voltage based on an output voltage is input; a first depletion transistor including a gate connected to the drain of the second transistor, and a source connected to a source of the second transistor; and a third transistor including a gate connected to the gate of the second transistor, and a drain connected to the drain of the second transistor.

Voltage regulator

Provided is a DC-DC converter including a soft start circuit capable of prolonging a soft start time without increasing a capacitance used in the soft start circuit. A soft start is implemented by gradually increasing a limiting level of an inductor current or a reference voltage. The soft start time is adjusted by varying a frequency of CLOCK signals supplied to switch circuits. The soft start time may be prolonged without increasing a chip size because the capacitance does not need to be increased to prolong the soft start time.

DC-DC converter with soft start circuit

Provided is a band gap constant-voltage circuit which is configured by combining a PMOS transistor, an NMOS transistor, a bipolar transistor, and a resistor, and is capable of preventing an output voltage from being stabilized at 0 V immediately after power supply fluctuation. According to the band gap constant-voltage circuit of the present invention, the back-gates of two p-type transistors (Pand P) constituting a differential amplifier are each connected to a node () which is a power source terminal on the positive side of the differential amplifier, and a level shifter circuit is connected to the gate of each of the transistors (Pand P).

Band gap circuit

Provided is a power supply switching circuit capable of efficiently supplying a desired voltage among a plurality of voltages to a load. In the case of a P-type semiconductor substrate, N-type MOS transistors are provided between a load and an AC adapter and between the load and a battery, and hence no parasitic diode exists between the load and the AC adapter or the battery, resulting in no current path due to the parasitic diode. Thus, when the AC adapter and the battery are connected to the power supply switching circuit, the N-type MOS transistor is turned off, whereby the current path between the battery and the load is cut off completely and the N-type MOS transistor is turned on. Accordingly, the battery cannot supply a voltage to the load while only the AC adapter can supply a voltage to the load.

Power supply switching circuit

A current detector circuit detects a current supplied to a load and generates as a detection result a voltage corresponding to the detected current. A first p-channel transistor has a source connected to a power supply and a gate connected to a ground, and is configured to allow the passage therethrough of a current that is 1/N of a current flowing through a transistor which drives the load. A second p-channel transistor has a source connected to a drain of the first p-channel transistor, and a third p-channel transistor is connected to the load. A voltage mirror circuit has first and second terminals connected to respective drains of the second and third p-channel transistors. A n-channel transistor has a drain connected to the drain of the first p-channel transistor and outputs a source voltage as the detection result of the current detector circuit.

Current detector circuit and current mode switching regulator

Provided is an adder in which all of circuits can be constituted by CMOS transistors, a process is simplified, and a chip size can be reduced as compared with a conventional art. The adder according to the present invention includes: a first VI converter and a second VI converter that allow a current corresponding to an input voltage to flow therein; and a current addition resistor having one end commonly connected to output terminals of the first VI converter and the second VI converter and another end grounded, which is adjustable in a resistance value. Each of the first VI converter and the second VI converter includes: a prestage VI converter that generates a reference current; a poststage VI converter that generates a current corresponding to the input voltage; a first current mirror circuit whose first terminal on a reference side is connected with the prestage VI converter and whose first output terminal in which a current corresponding to the first terminal flows is connected with the poststage VI converter; and a second current mirror circuit whose second terminal on the reference side is connected to the first output terminal, and which can adjust a current ratio from a second output terminal in correspondence with the current that flows in the second terminal. A voltage at the one end of the current addition resistor is output as an addition voltage.

Adder and current mode switching regulator

Provided is a band gap constant-voltage circuit capable of achieving a quick startup time to thereby preventing an output voltage from being stabilized at 0 V due to noise or the like even under the normal condition. The band gap constant-voltage circuit according to the present invention includes: an output voltage detecting circuit for monitoring a voltage at an output terminal; and a current source which has a current value controlled through an output of the output voltage detecting circuit, in which the current source supplies a bipolar transistor constituting a level shifter circuit with a current when the voltage at the output terminal is lower than a predetermined voltage.

Band gap constant-voltage circuit

A semiconductor device is provided in which: a parasitic capacitance between a drain and a supporting substrate is reduced; and a high electric field generated in the vicinity of the drain is relaxed and which has a high withstand voltage. A MOS transistor according to the present invention includes: a supporting substrate region in an SOT substrate; a buried insulating film formed on the supporting substrate region; a channel region formed on the buried insulating film; and first and second offset regions that are formed on the buried insulating film so as to be adjacent to the channel region on both sides thereof, and further includes an impurity diffusion region formed in a portion positioned below the second offset region in the supporting substrate region.

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Chiba, Japan

Osamu Uehara