Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Hitachi Power Systems, Ltd.

Osamu Ueda

Kenichi Arase

Shinichi Mori

Masayuki Yamashita

Kikuo Muramatsu

Namiki Moriga

Tsuyoshi Toyama

Nobuaki Andoh

Hiroyuki Hamana

Naoyuki Seki

Masahiko Ishikawa

Kohji Hayano

Katsuhisa Shigemoto

Each of the portions corresponding to the crossings of a plurality of first strip conductive layers serving as bit lines and a plurality of second strip conductive layers serving as word lines crossing the conductive layers at right angles is used as one memory cell. An oxide film is provided between the first strip conductive layers and the second strip conductive layers. The thickness of this oxide film is set in each memory cell according to stored data. Also a multi-value memory can be realized, since the amount of stored data in each memory cell is an arbitrary amount of 1 bit or more by making the stored data of a plurality of types of memory cells having different thicknesses in the tunnel oxide film 15 correspond to a plurality of different data. The size of each memory cell can be reduced since the occupying area of each memory cell on the semiconductor substrate is dependent on the width of the first strip conductive layer and the second strip conductive layer. An insulation film in which tunnel phenomenon is generated can be formed using conventional manufacturing technology.

Method of making a mask ROM using tunnel current detection to store data

Mask ROM using tunnel current detection to store data and a method of

In accordance with one aspect of the present invention, provided is a semiconductor device comprising a semiconductor chip which is directly covered with a resin material having a light shielding property as well as a film which is provided on the resin material for shielding the semiconductor device against light. The film may be formed by a seal having a surface which is covered with a metal and a rear surface which is colored black, a layer of a metal or ceramics which is deposited in a vapor phase, or a coating of an insulating material whose refractive index is different from that of the resin material. In another aspect of the present invention, provided is a semiconductor device which is directly covered with a resin material mixed with a light absorbing material. In still another aspect of the present invention, provided is a semiconductor device comprising a semiconductor chip, having a surface covered with black polyimide, which is further covered with a resin material having a light shielding property. In a further aspect of the present invention, provided is a package for covering a semiconductor device which is mounted on a wiring board. According to such improvement, a light shielding property is improved particularly in relation to a thin semiconductor device whose thickness is only about 1 mm, and the semiconductor device is prevented from a malfunction caused by light.

Semiconductor device improved in light shielding property and light

Provided is a semiconductor device comprising a semiconductor chip which is directly covered with a resin material having a light shielding property as well as a film which is provided on the resin material for shielding the semiconductor device against light. The film may be formed by a seal having a surface which is covered with a metal and a rear surface which is colored black, a layer of a metal or ceramics which is deposited in a vapor phase, or a coating of an insulating material whose refractive index is different from that of the resin material. In another aspect of the present invention, provided is a semiconductor device which is directly covered with a resin material mixed with a light absorbing material. In still another aspect of the present invention, provided is a semiconductor device comprising a semiconductor chip, having a surface covered with black polyimide, which is further covered with a resin material having a light shielding property. In a further aspect of the present invention, provided is a package for covering a semiconductor device which is mounted on a wiring board. According to such improvement, a light shielding property is improved particularly in relation to a thin semiconductor device whose thickness is only about 1 mm, and the semiconductor device is prevented from a malfunction caused by light.

Data processing system including memory device having even-numbered addresses and odd-numbered addresses in which both an even-numbered address and an odd-numbered address are accessed in the long data bit length mode and either an even-numbered address or an odd-numbered address is accessed in the short data bit length mode, comprising a switching circuit 200 for carrying out the data communication with an odd-numbered address through a high-order data bus 6 or a low-order data bus 5 in the short data bit length mode, and a switching circuit 150 for carrying out the data communication with an odd-numbered address through the low-order data bus 5 in both the long and short data bit length modes. By virtue of this structure, the data communication through the low-order data bus only is made possible for both an even-numbered address and an odd-numbered address in the short data bit length mode.

Method of and system for processing data having bit length variable with

A semiconductor storage device formed on a single chip includes a ROM, a RAM and an input/output port. When a mode setting signal designates a normal mode, access is made to one of the ROM, RAM and input/output port in response to an address signal. The ROM is accessed when the mode setting signal designates a ROM write mode and the address signal designates an address assigned to the ROM. A dummy data is output from a data input/output terminal when the mode setting signal designates the ROM write mode, the address signal designates an address outside an address region assigned to the ROM, and a read signal is applied to the device.

Composite semiconductor storage device and operating method therefor

A semiconductor memory device having an error correcting circuit includes a circuit for generating a desired test signal with which memory cells used for error correction are to be tested, and another circuit for judging on an chip-basis whether memory cells of the semiconductor memory device are normal or not. The memory cells for error correction can be tested accurately by application of desired test signal. In addition, since there is no necessity of provision of a circuit for comparing externally applied data and data delivered from the semiconductor memory device, a test can be preformed readily.

Semiconductor memory device having improved error correcting circuit

A non-volatile semiconductor memory device includes a substrate (1) having a plurality of element-forming regions (3), a plurality of recesses (32) located between the element-forming regions (3), and a plurality of element-isolating regions (31); word lines (8a to 8d); bit lines (10) orthogonal to this word lines; and memory cells (511) each formed at the point of intersection of these word and bit lines at each element-forming region (3). Each memory cell (511) includes an electrically floating electrode (5) in the form of a flat plate, a control gate electrode (7) in the form of a substantially flat plate formed on the floating gate electrode (5) and connected to the word lines (8a to 8d), and a pair of impurity regions (21, 23) formed respectively at opposite sides of the floating gate electrode (5) on the surface of a semiconductor substrate (1). An element-isolating region (31) includes an element-isolating electrode layer (30) formed on the surface of the semiconductor substrate (1) and in the recesses (32).

Electronic integrated circuit having an electrode layer for element

A multifunctional memory comprises a mask ROM (2). When an 'L' level signal is applied to a control pin (EXT), data is read out from the ROM (2) in response to an address signal inputted from a multiplex pin (AD/DA). Thereafter, the data read out from the ROM (2) is outputted from the multiplex pin (AD/DA). In this case, an 'H' level signal is outputted from a chip select pin (CS). When an 'H' level signal is applied to the control pin (EXT), an 'L' level signal is outputted from the chip select pin (CE). Consequently, the EPROM (30) is rendered active. In addition, the address signal inputted from the multiplex pin (AD/DA) is outputted from a port/address pin (PORT/AD). Data is read out from the EPROM (30) in response to the address signal.

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Hyogo, Japan

Osamu Ueda