Fujitsu Corporation

Osamu Tago

Takeshi Fuse

Atsushi Fujita

Yoshihiko Koike

Norihiro Nakatsuhama

Masaaki Tani

Shigeo Koide

Yukihiro Ozawa

Takashi Sugimoto

Toshiyuki Igarashi

An abnormality detection device detects an abnormality in a communication bus. The abnormality detection device comprises a timer counter connected to the communication bus so as to measure a time during which a signal having a first logical level is transmitted in the communication bus, and a comparator outputting an abnormality detection signal indicating an abnormality in the communication bus when the time measured by the timer counter surpasses a threshold value.

Abnormality detection device for detecting an abnormality in a communication bus

An apparatus for estimating a microcontroller for executing program estimation and system estimation of the microcontroller comprises, in an estimation device, a data holding unit for holding data rewritably; a processing unit for operating the microcontroller on the basis of a control signal and processing the data; an interface unit for external communication, for taking out the control signal from signals supplied from the external and sending it to the processing unit; and an internal bus monitoring unit for monitoring the state of an internal bus connecting mutually the data holding unit, the processing unit and the interface unit for external communication. This apparatus is constituted in such a manner that the data obtained by writing the state of the internal bus, ant the time when the microcontroller is operated, into the internal bus monitoring unit is inputted to the data holding unit, or is sent to the external, via the interface unit for external communication. A method of estimating a microcontroller is executed by using the apparatus having such a construction.

Apparatus for estimating microcontroller and method thereof

A clock signal generator circuit has a clock generator for generating clock signals to be supplied to a central processing unit and to functional blocks, and clock selectors. The clock generator divides the frequency of a source clock signal, to form a clock signal having an optional period. Namely, the clock generator suppresses at least one active or inactive state of the source clock signal, to generate a clock signal whose period is an integer multiple of that of the source clock signal. The clock selectors receive the clock signals generated by the clock generator and selectively supply them to the CPU and functional blocks. The clock signal generator circuit is capable of operating a microcontroller system at a required minimum speed, to optimize the power consumption of the system.

Clock signal generator circuit using a logical result of an output of a

A reload-timer/counter circuit provides a reload-timer function and a counter function commonly and selectively. The circuit is comprised of first, second, third, and fourth registers. The third and fourth registers act as a control status register and a mode register, respectively. The first and second registers act as, in the reload-timer mode a data register and a counter register, respectively, while in the counter mode, the first and second registers act as the counter registers.

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Kawasaki, Japan

Osamu Tago