Hitachi, Ltd.

Hitachi Computer Electronics Co., Ltd.

Osamu Tada

Yoshinobu Okazaki

Toshio Oguma

Kazunobu Morimoto

Mototsugu Fujii

Shun Ishiyama

Tatsuya Tochio

Shigeki Yokotani

Satoshi Fujiwara

Logic emulation according to the present invention is aimed at an object to provide a logic dividing and module wiring system for operating logic related to external interface signals and interface signals among circuits obtained as a result of division or a logic circuit at a high speed. In a logic emulation system, information on assignments of external interface signals of logic to connector pins is read in during division of the logic. Logic related to an external interface signal assigned to a connector pin is assigned to a field programmable gate array directly connected to the connector pin. In addition, delays are checked after the division of a logic circuit in order to determine the level of delay criticality of each interface signal between field programmable gate arrays. Wiring of a module is then carried out in accordance with the levels of criticality.

Logic dividing method, logic dividing system and recording medium for storing logic dividing program

A logic emulation system that verifies a target logic circuit and evaluates its performance efficiently divides the design data of a target logic circuit into a plurality of small-scale logic circuits and a connection circuit for interconnecting the small-scale logic circuits, thereby creating an equivalent circuit of the target logic circuit. The logic emulation system judges, when a logical design change to the target logic circuit prompts the comparison of the data of the equivalent circuit of the logic circuit before the logical change with the data after the logical change, whether it is feasible to implement the design data on the logically changed logic circuit by adding one or more small-scale logic circuits, and by altering the connection circuit accordingly. When the implementation of the design data on the logically changed logic circuit is judged to be feasible, the equivalent circuit of the logically changed logic circuit is generated by resorting to the above measures and without modifying the existing equivalent circuit.

Logic emulation system

A design support system for executing logic verification so as to perform work management, progress state management and logic quality management efficiently in a logic verification process and so as to improve the man-hour for development and the throughput of computer resources. For every verification item to be executed, management information including a verification item number for identifying a verification item, confirmation information for indicating the fact that no failure has been confirmed in the verification item, a prerequisite verification item number for identifying another verification item required to be confirmed as a prerequisite for the verification item is stored in a memory of the system. Before execution of logic simulation which is performed by giving test data for logic verification of the design data to the design data as a subject of logic verification, data in the memory are searched so that logic simulation is executed in the case where all verification items as prerequisites for verification items to be executed have been already confirmed.

Design support system and method therefor

A program data creating method and apparatus for use with programmable devices in a logic emulation system provides high-speed logic emulation of an LSI for logic and function verification. The logic data defining the logic circuits of the LSI is divided into a plurality of unit blocks in a layout analogous to the floor plan represented by floor plan information for the LSI. The unit blocks are allocated to the programmable devices automatically. The names of the signals defined within the design data regarding the LSI are made to correspond with the names of the signals in effect when the design data is deployed within the programmable devices, after optimization of the logic. This allows the program data for the programmable devices to be created and corrected using the signal names as set forth in the design data.

Program data creating method and apparatus for use with programmable

The electronic circuits of a large-scale ASIC or logic device are assigned to a plurality of programmable chips with logic block division that enables the finished circuits to operate at appropriate timings. A logic division processing unit divides the electronic circuits into a plurality of groups for automatic assignment to a plurality of programmable chips. A checking unit determines whether the designated logic blocks are accommodated in one programmable chip, and a division processing unit determines which logic blocks are to be assigned and the order of assignment priorities when the designated logic blocks are not all accommodated in the same programmable chip.

Logic division apparatus

A logic simulation system for simulating a quality of logic description of a tested electric circuit includes a storage for storing execution results of logic simulation which was conducted for the electric circuit in the past and for which operations of the circuit have been confirmed, logic description to be tested for the electric circuit, and test data of the logic description to be tested. Logic simulation is conducted according to the test data and the logic description to be tested. Results of the logic simulation are compared with the past logic simulation results of operation by correcting time values according to a predetermined rule so as to simulate quality of the logic description, thereby outputting quality of the logic description in a visible form.

Growing community of inventors

Hadano, Japan

Osamu Tada