Hitachi, Ltd.

Osamu Suga

Yoshinori Nakayama

Shinji Okazaki

A system and method are provided for compensating for proximity effects between selected adjacent portions of pattern elements on an integrated circuit wafer where it is determined by simulation that undesirable resist patterns will result. The subject lithography system includes projecting an electron beam onto the wafer through an aperture plate of pattern elements to obtain the desired beam pattern. An aperture mask includes a plurality of first portions corresponding to first wafer circuit element portions spaced for avoiding proximity effects on the wafer and a plurality of second portions corresponding to second element portions spaced for obtaining proximity effects between elements on the wafer. The plurality of second portions are sized to have an increased adjacent spacing relative to a resultant adjacent spacing of the corresponding second element portions whereby the resultant adjacent spacing of the second element portions on the wafer is selectively reduced by the proximity effects. Alternatively, or in addition, a wire mesh is provided at the second portions of the aperture plate to reduce the beam intensity for corresponding reduction of the proximity effects.

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Kokubunji, Japan

Osamu Suga