Sony Corporation

Saturn Licensing LLC

Osamu Shinya

Takashi Yokokawa

Satoshi Okada

Yuji Shinohara

Toshiyuki Miyauchi

Lachlan Bruce Michael

Naoki Yoshimochi

Yuichi Hirayama

Takashi Horiguchi

Kazuhiro Oguchi

Hitoshi Sakai

A data processing device and a data processing method that can readily process control data having its PAPR improved. In a transmission device, a padder pads control data necessary for demodulation with zeros as dummy data, and a scrambler scrambles the padded control data (post-padding control data). A replacement unit replaces scrambled dummy data in the scrambled post-padding control data with the dummy data, and a BCH encoder and an LDPC encoder perform BCH encoding and LDPC encoding as error correction encoding on the replacement data obtained through the replacement. A shortening unit performs shortening by deleting the dummy data contained in the LDPC code and puncturing the parity bits of the LDPC code. The device can be applied in cases where control data is subjected to error correction encoding and is then transmitted, for example.

Data processing device and data processing method

A receiving apparatus includes: an LDPC decoding device configured such that when an LDPC-coded data signal, LDPC representing Low Density Parity Check, and an LDPC-coded transmission control signal are transmitted in multiplexed fashion, the LDPC decoding device can decode both the data signal and the transmission control signal; a holding device configured to be located upstream of the LDPC decoding device and to hold at least the transmission control signal upon receipt of the data signal and the transmission control signal; and a control device configured to control the LDPC decoding device to decode the data signal while the transmission control signal is being accumulated in the holding device and to interrupt the current decoding so as to control the LDPC decoding device to decode the transmission control signal when the transmission control signal has been accumulated in the holding device.

Receiving apparatus, receiving method, program, and receiving system

A reception apparatus is disclosed which includes: a reception section configured to receive an orthogonal frequency division multiplexing signal known as an OFDM signal formed by modulating common packet sequences and data packet sequences, the common packet sequences being made up of packets common to a plurality of streams, the data packet sequences being constituted by packets unique to each of the plurality of streams; an acquisition section configured to acquire decoding information for decoding the original streams from the common packet sequences and the data packet sequences obtained by demodulating the received OFDM signal; and a search section configured to search for the common packet sequence needed to decode the original streams from the designated data packet sequence on the basis of the acquired decoding information.

Reception apparatus, reception method, program, and reception system

A receiver that receives an Orthogonal Frequency Division Multiplexing (OFDM) signal obtained by modulating a common packet sequence and data packet sequence. The common packet sequence is made up of packets common to a plurality of streams. The data packet sequence is made up of packets specific to one of the plurality of streams. The receiver sorts the common packet sequence, obtained by demodulating the received OFDM signal, in the time domain, and sorts the data packet sequence, obtained by demodulating the received OFDM signal, in the time domain. The receiver then switches the output for error correction from the one sorting over to the other sorting if, while the one sorting supplies its output to the error correction, the other sorting completes its input of a predetermined unit of information to be processed.

Receiver, receiving method, program and receiving system

A receiving apparatus includes: a first decoding means for performing, every time frame data in which an inner code and an outer code are used as error correction codes is transmitted thereto, decoding processing employing the inner code and outputting decoded data; a storing means for storing the decoded data; a second decoding means for applying decoding processing employing the outer code to the decoded data; and a control means for controlling storage and output of the decoded data in and from the storing means to suspend, while the control means causes the storing means to output first decoded data as the decoded data of a decoding result of first frame data to the second decoding means, when the first decoding means starts output of second decoded data as the decoded data of a decoding result of second frame data following the first frame data, the output of the first decoded data to the second decoding means and cause the storing means to store the second decoded data and, when the storage of the second decoded data ends, cause the storing means to resume the output of the first decoded data to the second decoding means.

Receiving apparatus, receiving method, computer program, and receiving system

A receiving apparatus including, an LDPC decoder configured to decode both of the data signal and the transmission control signal, a data signal input buffer arranged before the LDPC decoder and configured to hold the received data signal and a transmission control signal input buffer arranged before the LDPC decoder and configured to hold the received transmission control signal, and a controller configured to select one of the data signal held in the data signal input buffer and the transmission control signal held in the transmission control signal input buffer as a signal subject to decoding and transmit the selected signal to the LDPC decoder to make the LDPC decoder decode the signal subject to decoding.

Receiving apparatus and method and program for receiving and decoding a low density parity check code

A decoding apparatus includes a memory and a receiving unit and is adapted to decode data in units of codewords each including a parity part. The memory has a storage capacity capable of storing at least data with a length equal to the length of one codeword. The receiving unit receives, as received values, elements of a codeword in a bit-interleaved form, performs bit deinterleaving and parity permutating on the received values, and stores the resultant received values in the memory.

Decoding apparatus, decoding method, and decoding program

A decoding device and method for decoding an LDPC code with high accuracy while suppressing an increase of the scale of a device. A check node calculator () performs check node calculations including calculations of a nonlinear function &#x3c6;(x) and its inverse function &#x3c6;(x) of the nonlinear function so as to decode an LDPC code. A variable node calculator () performs variable node calculation of a variable node so as to decode the LDPC code. The check node calculator () has an LUT which receives a fixed-point quantized value expressing a numerical value with a fixed quantization width and outputs the result of the calculation of the nonlinear function &#x3c6;(x) as a semi-floating point quantized value which is a bit sequence expressing a numerical value with a quantization width determined by a part of a bit sequence and an LUT which receives a semi-floating point quantized value and outputs the result of the calculation of the inverse function &#x3c6;(x) as a fixed point quantized value. The invention can be applied to e.g., a tuner for receiving a satellite broadcast.

Decoding device and method

A decoding apparatus and method are capable of decoding LDPC codes with a high degree of precision while preventing the circuit scale of the decoding apparatus from increasing. A computation section carries out a first computation process corresponding to three check-node processes by making use of decoding intermediate results supplied from a decoding intermediate result storage memory by way of a cyclic shift circuit, and stores the result of the first computation process in a decoding intermediate result storage memory. A computation section carries out a second computation process corresponding to six variable-node processes by making use of decoding intermediate results supplied from a decoding intermediate result storage memory by way of a cyclic shift circuit, and stores the decoding intermediate result in the decoding intermediate result storage memory.

Decoding apparatus and decoding method

A decoding device for decoding an LDPC (Low Density Parity Check) code. The decoding device may include a first operation unit for performing a check node operation for decoding the LDPC code, the operation including an operation of a nonlinear function and an operation of an inverse function of the nonlinear function; and a second operation unit for performing a variable node operation for decoding the LDPC code. The first operation unit includes a first converting unit for converting a first quantization value assigned to a numerical value into a second quantization value representing a numerical value with a higher precision than the first quantization value, and a second converting unit for converting the second quantization value into the first quantization value.

Growing community of inventors

Kanagawa, Japan

Osamu Shinya