Hewlett-packard Development Company, L.p.

Globalfoundries Inc.

Other

Hewlett-packard Company

Hewlett-packard Development, L.p.

Osamu Samuel Nakagawa

Norman H Chang

Shen Lin

Weize Xie

Cullen Edwin Bash

Chandrakant D Patel

Abdlmonem H Beitelmal

Keunmyung Lee

Pavan Bashaboina

Xuejue Huang

Kenynmyung Lee

Yu Cao

Ikuo Sasaki

Moshtaque Yusuf

Koji Yanagitani

Toshinobu Banjo

Embodiments of the present invention include systems and methods of controlling reticle transmission. A process window for reticle transmission is received. For a given design, default fill cells of a default fill pattern are inserted in unused areas of an integrated circuit (IC). A pattern density is computed for each tile of an IC at each appropriate level, such as metallization levels and contact levels. An IC reticle transmission (RT) is computed for an area corresponding to an entire (or area of) IC or reticle. If the integrated circuit RT is outside of the process window, then the tiles that have an individual tile RT that is outside of the process window are identified and ranked into groups. Default fill cells in one group of tiles are replaced with replacement fill cells having an appropriate pattern and pattern density, and an updated IC RT parameter is computed until the updated IC RT parameter is within the process window.

Optimization of integrated circuits for a reticle transmission process window using multiple fill cells

A method includes defining an array including a plurality of unit cells, receiving unit cell density parameters in a computing apparatus, and defining a plurality of sub-arrays of unit cells using the computing apparatus. The computing apparatus defines density features disposed between adjacent sub-arrays. The computing apparatus generates density feature density parameters based on the unit cell density parameters and at least one density limit.

Cell array and density features with decoupling capacitors

A system and method to model and design a layout of an Internet Datacenter (IDC) for cooling. The IDC is defined as a collection of cells, the cells of the IDC are pre-characterized, an arrangement of the cells within the IDC is determined, and a profile for one or more parameters of interest for each cell are determined.

Designing layout for internet datacenter cooling

A system and method to reduce leakage power consumption of electronic devices. In addition to assigning threshold voltages, sizes of the transistors within the device may be varied to provide a range of options to meet the timing requirements while minimizing the leakage power consumption.

System and method to reduce leakage power in an electronic device

A method determines a plurality of clock delay values. Each delay value is associated with a delay element on a clock line leading to a clock sink in a synchronous circuit. The method determines an initial set of delay values and executes an optimization algorithm, beginning with the initial set of delay values, to arrive at a set of delay values that at least approximately meets an criteria while satisfying timing constraints associated with selected pairs of logically connected clock sinks. In a preferred form, the optimization algorithm is a genetic algorithm or a gradient descent algorithm. The genetic algorithm involves selecting parent sets of delay values, crossing over so as to produce a child set of delay values, mutating the child set of delay values, evaluating how well the child set of delay values meets the criteria, and conditionally discarding the child set on the basis of the evaluating step. The gradient descent algorithm involves perturbing the initial set of delay values, evaluating how well the perturbed set of delay values meets the criteria, and conditionally discarding the perturbed set on the basis of the evaluating step. If the perturbed set is not discarded, then the gradient descent algorithm adjusts the values of the perturbed set in the same direction relative to the corresponding values in the initial set.

System and method for determining a plurality of clock delay values using an optimization algorithm

A method reduces noise resulting from a current surge in a circuit. A plurality of loading elements, parallel with the circuit being protected, are connected sequentially and disconnected. The connection of the loading elements results in a ramping up of current through the circuit without a sudden surge. In a preferred embodiment, an apparatus for slowing a current change in a circuit is described. The apparatus comprises a plurality of loading elements placed in parallel with the circuit, each of the elements providing a path for current flow, and a control circuit for selectively opening or closing at least one of said paths to prevent or enable current flow through the at least one of the paths.

Method for reducing current surge using multi-stage ramp shunting

A logic gate circuit and related methods and apparatus exhibit reduced voltage swing and thereby consume less power. The circuit is connected to a plurality of input signals and a clock signal. The circuit produces an output. The circuit comprises a node, a pull-down network and an N-type MOS transistor. The pull-down network is connected to the node, a first reference voltage, the plurality of inputs and the clock signal. The N-type MOS transistor is connected between the node and a second reference voltage. The N-type MOS transistor is also connected to a complement of the clock signal. A method of the invention accepts a complement of a clock signal and pre-charges a node to a voltage less than a power supply voltage, in response to the complement of the clock signal. The method also accepts a plurality of input signals and accepts the clock signal. The method conditionally discharges the node, in response to the clock signal, on the basis of the plurality of input signals.

Partial swing low power CMOS logic circuits

A system and method is provided for controlling clock skew to meet timing constraints for a semiconductor integrated circuit. On-chip self-tuning circuits can be connected to each latch in the integrated circuit for controlling clock skew. Each self-tuning circuit delays a clock signal that is input to a latch when the clock skew does not satisfy the timing constraint for that latch. The self-tuning circuit repeatedly delays the clock signal until the clock skew is satisfied or until the delay becomes greater than or equal to a predetermined threshold. The delayed clock signal is then pushed to other latches in the integrated circuit until all the timing constraints for the integrated circuit are satisfied.

Parallel push algorithm detecting constraints to minimize clock skew

An RLC module is configured to provide a simplified circuit modeling of a selected circuit net (or portion) of an electronic circuit. The RLC module may be configured to substitute an RLC circuit model for the selected circuit net, where the effective values of the capacitance and inductance for the RLC circuit model are retrieved from a table of capacitance and inductance values. A set of interconnect geometry factors (e.g., line length, line width, driver/receiver length, etc.) that describes the circuit net is used as an index into the table of capacitance and inductance values. The retrieved values of the effective capacitance and inductances values may be used to calculate a delay for the RLC circuit model. The RLC module may provide the capability to quickly calculate a delay for a selected circuit net without using computationally intensive calculations for inductance and capacitance values of circuit nets.

System for improving circuit simulations by utilizing a simplified circuit model based on effective capacitance and inductance values

A ramp loading circuit for slowing current change in a circuit block. The circuit may include a plurality of load circuits placed in parallel with the circuit block and a control circuit. Each load circuit may provide a path for current flow when the load circuit is activated. Each load circuit may also be configured to allow a gradual decrease in current flow through the path when the load circuit is deactivated. The control circuit may be configured to deactivate each load circuit before the circuit block enters the sleep mode.

Ramp loading circuit for reducing current surges

A metal mold for plastic molding a semiconductor device by a transfer-molding method with the use of thermo-hardening plastics. The mold includes a pot section into which plastic is injected; a cavity section where a product is formed; a runner section constituting a path for the plastic from the pot section to the cavity section; a gate section provided between the runner section and the cavity section so as to reduce the cross-sectional area for the flow of the plastic which flows therethrough from the runner section to the cavity section; and a flow restrictor section provided in the path of the runner section so as to reduce the cross-sectional area of the flow of plastic.

Growing community of inventors

Redwood City, CA, United States of America

Osamu Samuel Nakagawa