Hitachi, Ltd.

Osamu Onodera

Ken Uehara

Yuji Kobayashi

Hideaki Amano

Makiko Shinohara

Kiichi Sato

A storage unit comprises a plurality of storage modules, each of which is dynamically assigned to and used as each area in a main storage (MS) or an extended storage (ES). The storage unit or a system controller has address arrays for MS and for ES which store information indicating which of the storage modules comprised in the storage unit each area in the MS and the ES corresponds to. When the contents of the MS/ES address arrays are rewritten to change a storage module belonging to the ES to a storage module belonging to the MS, a page-in operation is realized without executing an actual data move operation. Similarly, a page-out operation is realized without executing an actual data move operation by changing a storage module belonging to the MS to a storage module belonging to the ES.

Method of processing a data move instruction for moving data between main storage and extended storage and data move instruction processing apparatus

Method of processing a data move instruction for moving data between

A connection method of a plurality of input/output channels between a plurality of sub-channels of an information processing system having a virtual machine running on a physical machine under control of a hypervisor and a plurality of devices. The method includes issuing from the hypervisor a command for setting configuration information defining a plurality of configuration structures between the sub-channels set for the respective virtual machines and the devices in a storage device and acquiring configuration information containing the sub-channel corresponding to a designated device from the configuration information corresponding to one of the virtual machines based on the device designation contained in the input/output command from the one virtual machine. The virtual machines are enabled after the issuance of the set command and before the issuance of the input/output command. The corresponding configuration information is searched by using ID information of the virtual machine which issued the input/output command in order to execute the step so that one of a plurality of channel paths between a plurality of devices and the sub-channels is selected to execute the input/output designated by the input/output command.

Method and apparatus for connecting i/o channels between sub-channels

A virtual machine system capable of considerably improving its performance by preventing a variation of time slice values of logical processors and strictly ensuring the concurrent running of a plurality of logical processors belonging to the same virtual machine, in the configuration and management of virtual machines of a multi-processor structure having a plurality of logical processors. A method of controlling a virtual machine running time in the virtual machine system includes collectively storing time slice values of logical processors in a virtual machine to which the logical processors belong, and making a virtual machine control program for supervising and controlling the logical processors to store and manage the time slice values.

Control method for virtual machine running time in virtual machine system

An extending system in an information processing system which includes an input/output channel and operates a plurality of virtual computers. A plurality of input/output processing units are included in the input/output channel and each virtual computer issues a region ID and a channel path ID. A channel path reconfiguration array is provided having a plurality of channel path reconfiguration array blocks corresponding to region IDs. Each channel path reconfiguration array block includes a plurality of channel path reconfiguration array entries corresponding to channel path IDs and each channel path reconfiguration array entry includes an input/output processing unit number and a channel path ID. A selector is provided for selecting a channel path reconfiguration array block corresponding to the region ID issued by a virtual computer and selecting a channel path reconfiguration array entry corresponding to channel path ID issued by the virtual computer within the selected channel path reconfiguration array block. The virtual computer selects one of the input/output processing units corresponding to the input/output processing number from the selected channel path reconfiguration array entry and accesses the input/output processing circuit using the channel path ID from the selected channel path reconfiguration array entry.

Extending system of input/output channel

An apparatus and method for controlling the reconfiguration of the physical storage area in a real storage device employed by an information processing system. The invention includes an address reconfiguration array having a plurality of storage blocks which are each assigned to a virtual computer. Each storage block is composed of a plurality of host real-address entries. Assigned to a storage area in the logical memory of a virtual computer, each host real-address entry includes a validity field containing a validity bit and a host real-address field containing a high-order part of the start address of a real storage segment allocated to the storage area. The invention also includes a selector which receives the identifier of a virtual computer and a logical address from the virtual computer, and makes use of the identifier for choosing a storage block from the address reconfiguration array and a high-order portion of the logical address for selecting a host real-address entry from the chosen storage block. The value of the host real-address field of the selected host real-address entry, the high-order part of a real address, is then read out from the selected host real-address entry, and is merged with the low-order portion of the logical address in order to create a real address. If the validity bit indicates that the contents of the host real-address entry are invalid, however, the virtual computer is interrupted. A change to the contents of the address reconfiguration array can be made by replacing the contents of a host real-address entry chosen by the selector with update data.

Method and apparatus for controlling reconfiguration of storage-device

When virtual machines are activated under a condition in which an assignment request having a storage extent and a storage region origin is designated and an assignment request having only the storage extent designated are mixedly present, the logical partion (LPAR) whose storage origin is designated by flags is regarded as already assigned even when the storage region is not actually assigned, and a work table indicative of the current status of the storage assignment is generated in a not-in-use storage region table. The not-in-use storage region table is generated on the basis of the work table to determine the assignment or non-assignment of the LPAR to be activated, and assignment or non-assignment of a plurality of such not-in-use regions can be judged in an ascending order.

Storage region assignment method in a logically partitioned environment

A method fr purging a translation lookaside buffer purges only those entries required to be purged in order to eliminate overhead incurring degradation in the use efficiency of the translation lookaside buffer. The buffer is employed in a virtual machine system containing a plurality of levels of virtual machines and at least one register for storing virtual machine identification codes. Upon execution of an instruction, which is issued by a particular one of the virtual machines and which is accompanied by a purge of the translation lookaside buffer, the virtual machine identification code of the particular virtual machine and a virtual machine identification code of another virtual machine having a translation lookaside buffer entry to be purged are stored in the register. When the instruction is executed, the entry storing the virtual machine identification code which coincides with that of the particular virtual machine is purged, while the entry storing the virtual machine identification code which coincides with that of the other virtual machine is purged in parallel.

Method of parallel purging of translation lookaside buffer in a

A level-2 virtual machine is constructed under the control of a level-1 operating system (OS) operating on a real machine (level-1), and a level-3 virtual machine is constructed under the control of another operating system (OS) operating on the level-2 virtual machine. A level-3 virtual address generated in the level-3 virtual machine is translated to a level-2 virtual address, which is further translated to a level-1 virtual address. A third predetermined main storage address is added to the level-1 virtual address to generate a level-1 absolute address. The translated address is checked as to whether it is within a predetermined area on the main storage.

Virtual machine and method for controlling the same

A virtual machine system controls the operation of a plurality of virtual machines on a single computer and permits the computer to be switched from one virtual machine to another for carrying out urgent input/output operations. The decision to switch from an operating virtual machine to one of a plurality of other non-operating virtual machines is based on examining the number of input/output interrupt conditions that occur for each virtual machine other than the running one. When the number of input/output interrupt conditions for a virtual machine other than the running one is found to exceed a predetermined threshold number, operation of the currently running virtual machine is suspended. Control of the computer is then returned to the virtual machine control system to permit execution of another virtual machine so that the input/output interrupt condition for that virtual machine can be acknowledged.

Virtual machine I/O interrupt control method compares number of pending

Virtual address translation in three level virtual machine

A data processing apparatus for performing decimal arithmetic operation with the aid of a decimal arithmetic unit having an operation width corresponding to a plurality of bytes. Length value of an operand which is to undergo arithmetic operation of the decimal arithmetic unit is held in an operand length register, while a byte position which constitutes the least significant position in the arithmetic operation is held in an operand point register. An overflow detection controlling circuit generates a control signal in accordance with the contents in both the registers. An overflow detecting circuit detects presence or absence of an overflow by checking a particular byte contained in the output of the decimal arithmetic unit, the particular byte being designated by the control signal produced from the overflow detection controlling circuit.

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Hadano, Japan

Osamu Onodera