Hitachi, Ltd.

Sony Corporation

Other

Micron Technology Incorporated

Elpida Memory, Inc.

Ati Technologies Ulc

Ati Technologies Inc.

Hitachi Vlsi Engineering Corp.

Lixil Corporation

Maxim Japan Co., Ltd.

Hitachi, Ltd., Intellectual Property Group

Osamu Nagashima

Takeshi Sakata

Kazuhiko Kajigaya

Hiromasa Noda

Yoichi Miyajima

Kiyoo Itoh

Masashi Horiguchi

Masakazu Aoki

Hiroaki Sato

Toshio Takeshita

Kei Tashiro

Dean D Gans

Satoru Hanzawa

Yoshiro Riho

Grigori Temkine

Masatoshi Hasegawa

Riichiro Takemura

Hisashi Aoki

Toshiaki Ueda

Hiroki Fujisawa

Yoshinori Matsui

Tomonori Sekiguchi

Atsushi Takahashi

Atsuhiro Kumagai

Yoshinobu Nakagome

Hiroki Takahashi

Hitoshi Tanaka

Seiji Narui

Shinichi Miyatake

Hideyuki Sato

Mitsuaki Katagiri

Hideki Osaka

Katsuyuki Sato

Ichiro Anjo

Youji Idei

Sadayuki Morita

Shunichi Saito

Takahiro Sonoda

Haruko Tadokoro

Joseph D Macri

Olge Drapkin

Tomonori Watanabe

Mieko Hara

Takayoshi Yamasaki

Shoichi Shintani

Hideki Kamiya

Shouji Tatehata

Tatsuya Sakamoto

Hiroshi Ichikawa

Yukio Tsuchiya

Kan Takeuchi

Yasunobu Aoki

Katsumi Matsuno

Tsuyuki Suzuki

Masafumi Ohi

Tetsuo Ado

Tsutom Takahashi

Tatemi Ido

Koji Umetsu

Hitoshi Kawaguchi

Yasunori Yamaguchi

Makoto Morino

Yosuke Yukawa

Keun Soo Song

Toshihiro Koide

Akiko Hikita

Masahiro Yoshida

Toshiyuki Okada

Masanao Sato

Yoshihiro Sato

Masatsugu Honma

Masashi Miura

Tetsuya Saeki

Ryuji Nakamichi

Kazuhiko Kajiyama

Terutaka Okada

Jun Mitake

Norifumi Isu

Joseph Dominic Macri

A clock generator circuit may generate internal data clock signals, such as quadrature phase clock signals, based at least in part, on one clock signal responsive, at least in part, to another clock signal. The internal data clock signals may be generated from a system clock signal responsive to a data clock signal. The internal data clock signal may be generated by sampling the system clock signal. The sampling may be performed responsive to the data clock signal. A latch may latch a state of the system clock signal responsive to the data clock signal. The latch may output the internal data clock signal.

Apparatuses and methods for generating clock signals

Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.

Memory devices with multiple sets of latencies and methods for operating the same

A training operation may be performed by a memory controller to provide a system clock signal and a data clock signal having a desired temporal (e.g., phase) relationship to one another. The system clock and data clock signals may be provided to a memory. In some examples, the memory controller may provide a command to the memory to put the memory in a training mode. Once in the training mode, the memory controller may provide a write command and toggle the data clock signal a number of times. If the memory provides one output, the memory controller may adjust the relationship between the data clock and system clock signals. If the memory provides another output, the memory controller may maintain the relationship between the data clock and system clock signals and exit the training mode.

Apparatuses and methods for training operations

Erroneous insertion of a battery into an imaging device is prevented. In a battery loading and unloading mechanism, a battery is formed with projecting portions at longitudinal both ends of a back surface and along back surface, the back surface being a surface opposite to an insertion surface of the battery, whereby even the battery formed in a flat rectangular parallelepiped and having the almost-square main surface can be prevented from being erroneously inserted into the device. The projecting portion has an inclined surface acutely inclined with respect to the back surface, and when the battery is unloaded from the device, unloading of the battery from the device is accelerated by the inclined surface undergoing contact pressure of the retaining means.

Battery loading and unloading mechanism

The invention is intended to easily enhance both the stain-resistant property against water scale and the stain-resistant property against oily components, in sanitary ceramic wares and the like which are brought into contact with water containing soluble silica as well as oily components. The stain-resistant coating material of the invention contains a main agent formed from a perfluoropolyether, and a solvent including an alkane and an alcohol, while the alkane has mean molecular weight of 138 to 180 g/mol.

Stain-resistant coating material and product having glass layer

A secondary battery for an electronic appliance, including a battery cell. The battery cell has a positive electrode, a negative electrode, and an electrolyte in a pack. A positive electrode terminal and a negative electrode terminal are led out from the same side face of the pack. A metallic battery can accommodates the battery cell therein such that the side face from which the positive electrode terminal and the negative electrode terminal are lead out is faced towards the opening side. A lid, made of a synthetic resin, in which terminal parts to be connected to the electrodes of the electronic appliance upon being connected to the positive electrode terminal and the negative electrode terminal are faced outwardly, plugs the opening of the battery can, the battery cell being accommodated in the battery can upon being adhered onto an inner face thereof.

Secondary battery

In a battery loading and unloading mechanism, a battery formed in a flat rectangular parallelepiped and having an almost square main surface is loaded and unloaded to and from a device. The battery is formed with projecting portions at longitudinal both ends of a back surface thereof and along the back surface, whereby the battery can be prevented from being erroneously inserted into the device. The projecting portion has an inclined surface acutely inclined with respect to the back surface, and when the battery is unloaded from the device, unloading of the battery from the device is accelerated by the inclined surface undergoing contact pressure of the retaining means. The device is formed with a notched portion which is adapted to expose the other projecting portion of the battery when the battery is loaded, thereby facilitating unloading of the battery.

A secondary battery for an electronic appliance, including a battery cell. The battery cell has a positive electrode, a negative electrode, and an electrolyte in a pack. A positive electrode terminal and a negative electrode terminal are lead out from the same side face of the pack. A metallic battery can accommodates the battery cell therein such that the side face from which the positive electrode terminal and the negative electrode terminal are lead out is faced towards the opening side. A lid, made of a synthetic resin, in which terminal parts to be connected to the electrodes of the electronic appliance upon being connected to the positive electrode terminal and the negative electrode terminal are faced outwardly, plugs the opening of the battery can, the battery cell being accommodated in the battery can upon being adhered onto an inner face thereof.

A battery pack, a battery charger, a method for charging a battery pack are provided. The battery pack includes a secondary battery, a switch element for controlling charging and discharging the secondary battery, a controller for controlling the switch element, and a communication unit for performing with a battery charger. During charging, an initial charging is switched to a quick charging when a voltage of the secondary battery reaches a predetermined voltage, and the battery charger judges the battery pack as abnormal when the voltage does not reach the predetermined voltage within a timeout period after the initial charging is started. At least one of the timeout period and the predetermined is stored. At least one of the timeout period and the predetermined voltage to be read out is transmitted through the communication unit to the battery charger.

Battery pack, battery charger and charging method having multiple charging modes

The present invention provides a charging apparatus capable of efficiently charging battery in view of power consumption and a charging method. The charging apparatus has a charging unit which charges a battery, a remaining capacity detecting unit which detects remaining capacity of the battery, a necessary charging capacity obtaining unit which obtains charging capacity necessary for use after completion of the charging of the battery, an additional charging capacity calculating unit which calculates additional charging capacity for additionally charging the battery based on the remaining capacity and the necessary charging capacity of the battery, a charging current determining unit which determines a charging current at the time when the charging unit charges for the additional charging capacity based on power consumption generated at the time of charging for the additional charging capacity, and a control unit which controls the charging unit based on the determined charging current.

Charging apparatus and charging method

Growing community of inventors

Hamura, Japan

Osamu Nagashima