Toshiba Memory Corporation

Fujitsu Corporation

Fujifilm Corporation

Kioxia Corporation

Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Kabushiki Kaisha Toshiba

Osamu Matsuura

Hideki Inokuma

Masanari Fujita

Takeshi Imamura

Kenichi Fujii

Kenji Maruyama

Kazuaki Takai

Genki Kawaguchi

Taichi Iwasaki

Hideo Wada

Hajime Kaneko

Takanobu Itoh

Makoto Watanabe

Tomoyuki Takahashi

Takuya Inatsuka

Katsuyoshi Asakura

Yu Hirotsu

Wataru Sakamoto

Katsuyoshi Matsuura

Hisashi Kato

Shigeyoshi Umemiya

Kazuhiro Nojima

Yoshimasa Horii

Masaaki Hatano

Shoichi Miyazaki

Kazuya Taniguchi

Sota Matsumoto

Kazuo Ohno

Akira Yotsumoto

Kanako Shiga

Mitsunori Masaki

Masanori Fujita

Satoshi Tatara

Ayumi Watarai

Semiconductor memory device includes: a first and second member each extending in a first direction in a boundary part between a first and second block region and arranged in the first direction; a support pillar arranged between the first and second member at the boundary part; conductive layers separated from one another and arranged in a third direction and split by the first and second member, and the support pillar into a first and second portion; and a memory pillar penetrating through the conductive layers. The support pillar includes a lower and upper pillar. A side face of the lower pillar and an extension of a side face of the upper pillar are displaced from each other in a plane based on a second and the third direction.

Semiconductor memory device

A semiconductor memory device according to an embodiment includes a substrate, a source line, word lines, a pillar, an outer peripheral conductive layer, a lower layer conductive layer, and a first contact. The substrate includes a core region and a first region. The outer peripheral conductive layer is provided to surround the core region in the first region. The outer peripheral conductive layer is included in a first layer. The lower layer conductive layer is provided in the first region. The first contact is provided on the lower layer conductive layer to surround the core region in the first region. An upper end of the first contact is included in the first layer. The first contact is electrically connected to the outer peripheral conductive layer.

A semiconductor device according to an embodiment includes an N-well region, a first gate electrode, a single-crystal first semiconductor, and a first contact. The N-well region includes two P-type impurity diffusion regions. The first gate electrode is provided above the N-well region between the two P-type impurity diffusion regions. The first gate electrode is opposed to the N-well region via a gate insulating film. The single-crystal first semiconductor is provided in a columnar shape on the P-type impurity diffusion region. The first contact includes a polycrystalline second semiconductor. The second semiconductor is provided on the first semiconductor and includes P-type impurities.

Semiconductor device

According to one embodiment, a semiconductor device includes a transistor having a diffusion layer extending along a surface of a substrate and a gate electrode arranged above the diffusion layer; and contacts having elongated bottom surfaces connected to the diffusion layer on both sides of the gate electrode, in which the contacts are arranged so that the bottom surfaces of the contacts are not aligned in a straight line with an extension direction of the diffusion layer.

Semiconductor device and nonvolatile memory

A semiconductor memory device includes a stacked body, a semiconductor member, and a first insulating member. Electrode films and insulating films are alternately stacked along a first direction in the stacked body. An end part of the stacked body is shaped like a staircase in which a terrace is formed for each of the electrode films. A portion of the electrode film placed in the end part is thicker than a portion of the electrode film placed in a central part of the stacked body. The semiconductor member extends in the first direction and penetrates through the central part of the stacked body. The first insulating member extends in the first direction and is provided in the end part.

A semiconductor device according to an embodiment includes an N-well region, a first gate electrode, a columnar epitaxial layer, and a first contact. The N-well region includes two P-type impurity diffusion regions. The first gate electrode is provided above the N-well region between the two P-type impurity diffusion regions. The first gate electrode are opposed to the N-well region via a gate insulating film. The columnar epitaxial layer is provided on the P-type impurity diffusion region. The epitaxial layer includes a first semiconductor layer including P-type impurities. The first contact is provided on the first semiconductor layer of the epitaxial layer.

According to one embodiment, it includes a stacked body including N-number of layers (N is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing M-number of layers (M is an integer of 1 or more and (N&#x2212;2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.

Three-dimensional semiconductor memory device including slit with lateral surfaces having periodicity

A semiconductor memory device according to the embodiment includes a substrate, electrodes, at least one pillar structure, at least one charge storage film, and at least one insulating member. The electrodes are provided on the substrate, are separately stacked each other, and constitute a stacked body. The electrodes have a first width in a first direction along a surface of the substrate and include a portion extending in a second direction crossing the first direction along the surface. The pillar structure is provided in the stacked body and includes a semiconductor layer extending in a stacking direction of the stacked body. The charge storage film is provided between the semiconductor layer and the electrodes. The insulating member has a width in the first direction smaller than the first width, pierces the electrodes, and is provided to extend in the stacking direction.

Semiconductor memory device and method for manufacturing the same

According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a pillar structure, at least one charge storage film, and a first electrode. The stacked body includes electrode films stacked separately from each other. The pillar structure is provided in the stacked body and includes a semiconductor layer extending in stacking direction of the stacked body. The charge storage film is provided between the semiconductor layer and the electrode films. The first electrode is provided in the stacked body, spreads in the stacking direction and a first direction along a surface of the substrate, and contacting the substrate. The first electrode includes a first portion containing a material having conductivity and a second portion containing a material that a linear expansion coefficient is lower than a linear expansion coefficient of silicon, and positioned at a substrate side than the first portion in the stacking direction.

According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, and a plurality of columnar parts. The stacked body is provided on the substrate. The stacked body includes a plurality of electrode films stacked separately from each other. The plurality of columnar parts is provided in the stacked body. Each of the plurality of columnar parts includes a semiconductor pillar extending in a stacking direction of the stacked body, and a charge storage film provided between the semiconductor pillar and the stacked body. The plurality of electrode films includes a first electrode film provided in upper layers of the stacked body and a second electrode film provided in lower layers of the stacked body. A thickness of the first electrode film is thicker than a thickness of the second electrode film. The first electrode film is provided with a void.

A semiconductor device according to embodiments described below includes an element region and a peripheral region. The element region is disposed on a substrate and semiconductor elements are collocated in the element region. The peripheral region is disposed on the substrate and surrounds the element region. The element region extends in a first direction parallel to the substrate and includes a plurality of wiring layers laminated on the substrate. The peripheral region includes a peripheral layer arranged to surround the element region. The peripheral layer includes a first part extending in the first direction and a second part extending in a second direction intersecting the first direction. The cross-section structures of the first part and the second part are different from one another.

A semiconductor device includes a transistor formed on a semiconductor substrate, a first insulation film formed above the semiconductor substrate, and first and second capacitors located on the first insulation film. The first capacitor includes a lower electrode, a ferroelectric, and an upper electrode. One of the lower electrode and the upper electrode is connected to an impurity region of the transistor. The second capacitor includes a first electrode, a first dielectric, a second electrode, a second dielectric, and a third electrode. The lower electrode is formed from the same material as the first electrode, the ferroelectric is formed from the same material as the first dielectric, and the upper electrode is formed from the same material as the second electrode.

Semiconductor device and method for manufacturing semiconductor device

A semiconductor substrate with an insulating film, a barrier layer containing a metal and formed over the insulating film in a region that includes a peripheral edge part of a semiconductor substrate, a capacitor lower electrode layer formed on the barrier layer and having an edge-cut on the peripheral edge part of the semiconductor substrate, an oxide layer formed on the barrier layer at the peripheral edge part where the barrier layer is not covered by the lower electrode layer, a ferroelectric layer formed on the lower electrode layer and the oxide layer, and a capacitor upper electrode layer formed over the ferroelectric layer.

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Kuwana, Japan

Osamu Matsuura