Kabushiki Kaisha Toshiba

Jgc Corporation

Japan Com Company, Ltd.

Osamu Matsumoto

Isao Abe

Masayuki Yoshida

Yukihiro Saeki

Tomohisa Shigematsu

Nobuyoshi Chida

Koichi Ito

Hiroaki Kobayashi

Yasoji Suzuki

Yuji Nakano

Akira Takiba

Kazuyoshi Shinada

Tadashi Maruyama

Yasuhiko Shimizu

Hiroyoshi Murata

Ichiro Kobayashi

Noboru Hashimoto

Teruo Uemura

Shinichi Tokuda

Takeshi Nakashiro

Kenji Toyoda

Takahide Mizutani

Kenjiro Kanayama

Kazuhiko Miki

Tadashi Yabuta

Mika Saeki

Hiroyuki Takamura

Sachiko Shibuya

Eishirou Take

A spare decoder has a first register, a second register, and a multiplexer for selecting the output of the first register or that of the second register. The first register stores data of a fuse element. In the ordinary operating mode, a defective memory cell is replaced by a spare cell in accordance with the data stored in the first register. In the test mode, it is determined whether at least one spare cell is defective or not. If there are no defective spare cells, the data that should be stored in the defective memory cell is written into one of the spare cells. Further, the address of the defective memory cell is written into the second register. The defective memory cell is replaced by one of the spare cells in accordance with the data stored in the second register, by cutting the fuse element in accordance with the address of the defective memory cell.

Semiconductor memory device having both redundancy and test capability

In the memory cell matrix of a semiconductor integrated circuit device having a non-volatile semiconductor memory cell portion and a logic portion, a second-layered Al wires are formed on the first-layered Al wires, with an interlayer insulating film interposed therebetween. The pattern of the second-layered Al wires is the same as that of the first-layered Al wires. This structure reduces the labor for designing mask data, and increases the coating ratio of a resist to an Al layer while minimizing a reduction in the transmittance of ultraviolet ray. As a result, the amount of a reaction compound supplied from the resist into the Al layer for forming the second-layered Al wires increases, which prevents the second-layered Al wires from being undercut. Thus, the second and subsequent-layered Al wires of the logic portion can be effectively prevented from being thinned.

Semiconductor device having a memory cell portion and a logic portion

An aqueous high concentration coal slurry having a high dispersion stability is produced by a process in which a coal material is wet pulverized at a low concentration in a dispersing agent-free aqueous medium, the resultant coal slurry is hydrated, the dehydrated coal cakes are mixed with an aqueous dispersing additive solution to provide an aqueous coal slurry (A), a portion (B) of the slurry (A) is further pulverized, and the pulverized portion (B) is mixed with the remaining portion (D) of the slurry (A), or by a process in which a coal material is pulverized in an aqueous dispersing agent solution to provide a slurry moiety (E), separately a cake moiety (E) is provided, the slurry moiety (E) is mixed with the cake moiety (E) the above-mentioned process being carried out to an extent such that the resultant coal slurry contains coal particles having a size of 5 .mu.m or less in a content of 15% by weight or more and coal particles having a size of 500 .mu.m or less at a particle size distribution in which a variation coefficient C in size of the coal particles is 0.3 to 0.75.

Process for producing an aqueous high concentration coal slurry

The present invention relates to a precharge/discharge nonvolatile memory circuit for detecting signals output from two bit lines on read-cell and dummy cell sides using a flip-flop circuit, comprising a first row decoder on the read-cell side, a second row decoder on the dummy-cell side, a first column decoder on the read-cell side, a second column decoder on the dummy-cell side, a read cell selected by the first row decoder and the first column decoder, a dummy cell selected by the second row decoder and the second column decoder, first and second precharge transistors for performing a precharge operation, first and second discharge transistors for performing a discharge operation, the flip-flop circuit, a discharge control circuit for generating a discharge signal, and a precharge control circuit for generating a precharge signal after the discharge signal is generated from the discharge control circuit.

Nonvolatile memory circuit

A manufacturing method of a semiconductor memory device includes the steps of selectively forming a field oxide film and a gate oxide film on a semiconductor substrate, depositing a first conductive layer on an entire surface of the resultant structure, selectively etching the first conductive layer located in a region other than an element region, depositing a second conductive layer on an entire surface of the resultant structure, and etching the first conductive layer and the second conductive layer using the same mask to form a plurality of floating gates by the first conductive layer and to form a plurality of control gates by the second conductive layer, wherein the step of selectively etching the first conductive layer includes the first etching step of forming cell slits for separating the plurality of floating gates from each other and the second etching step of forming removed regions each of which includes only one end of each of the plurality of control gates.

Manufacturing method for a floating gate semiconductor memory device by

A potential detecting circuit comprises a first MOS transistor of a first conductivity type whose drain receives an input potential that is equal to or lower, in absolute value, than a second potential whose absolute value is higher than that of a first potential, a second MOS transistor of a second conductivity type whose source is connected to the source of the first transistor and gate receives the first potential, a third MOS transistor of the first conductivity type whose source is connected to the second MOS transistor, source receives a reference potential whose absolute value is lower than that of the first potential, and gate receives the first potential, a detecting potential control block for applying to the first MOS transistor a potential varying in accordance with the input potential, and a potential detect output terminal for providing a detected potential, the potential detect output terminal being a junction between the drains of the second and third MOS transistors.

Potential detecting circuit

Memory cells providing a memory cell array are each fromed of a floating gate MOS transistor for storing data and a select MOS transistor and the memory cell is connected to a power source via a MOS transistor providing a load element. A potential on the connection node A between the load element and the memory cell is detected by an inverter providing a potential detection circuit and a monitor output is derived from the inverter. A load providing MOS transistor having a source connected to the source of the MOS transistor providing the load element and a gate connected to the gate of the MOS transistor providing the load element is provided, a pad to which a control voltage is supplied is connected to the drain of the MOS transistor and the control voltage from the pad is applied to the gates of the MOS transistors to provide a current mirror circuit.

Semiconductor memory device having monitoring function

A non-volatile semiconductor device includes word lines, and a non-volatile memory cell array having a plurality of non-volatile memory cells respectively connected to the word lines. The non-volatile semiconductor memory device further includes a level shifter for receiving, in a programmming mode, an address signal supplied from outside, and shifting the potential level of the address signal to a higher programming potential level, and a row decoder, provided between the word lines and the level shifter, for receiving and decoding the address signal which has been shifted by the level shifter, and selecting one of the word lines in accordance with the result of the decoding of the address signal, and setting the potential of the selected word line to the programming potential level.

Non-volatile semiconductor memory device having, at the prestage of an

A sense amplifier includes a first P channel MOS transistor connected between a power source terminal and a bit line, and a CMOS inverter for inverting the logic level of the potential in the bit line. The sense amplifier further includes a second N channel MOS transistor connected in series to the first P channel MOS transistor between the power source terminal and the bit line. The second N channel MOS transistor is switch-controlled by an output signal of a CMOS inverter. When in an off state, the second N channel MOS transistor prohibits the first P channel MOS transistor from transferring a power source potential to the bit line. When in an on state, the second N channel MOS transistor allows the first P channel MOS transistor to transfer the power source potential to the bit line.

Sense amplifier having pull-up circuit controlled by feedback

An ultrasonic wire bonder includes first and second ultrasonic wave applying devices, the direction of vibration of the first ultrasonic wave being orthogonal to that of the second ultrasonic wave. One of the first and second ultrasonic waves or a composite ultrasonic wave thereof is applied to a capillary and/or a support base for wire bonding, depending upon the bonding direction along which a wire is extended, or the inner lead longitudinal direction. A unit for detecting the positions of a semiconductor chip and lead frame may be provided to adjust a position and control the ultrasonic wave to be applied.

Ultrasonic wire bonder

A memory cell of a nonvolatile semiconductor memory device includes a P conductive type semiconductor substrate, first and second diffusion layers of an N conductivity type, formed in the substrate, a channel region formed in the surface region of the substrate, and which is located between the first and second diffusion layers, a floating gate electrode formed on the channel region, and a control gate electrode formed on the floating gate electrode. The memory cell further includes a third diffusion layer of the N conductivity type, and formed between the first layer and the channel region, the third layer having an impurity concentration lower than that of the first layer.

Nonvolatile semiconductor memory device with a double gate structure

A sense amplifier of the invention includes a PMOS transistor, the source and the drain of which are respectively connected to a power source and an EP-ROM as a signal source to be detected, and the gate and the drain of which are controlled to be at the same potential, a PMOS transistor connected to the power source and the EP-ROM in parallel with the PMOS transistor, and a ratio circuit in which the gate of one PMOS transistor and an NMOS transistor constituting a CMOS transistor is connected to the signal source. This arrangement of the invention enables a high speed operation.

Growing community of inventors

Yokohama, Japan

Osamu Matsumoto