Fujitsu Corporation

Fujitsu Semiconductor Limited

Osamu Kudo

Shinya Udo

Masao Kumagai

Hideto Fukuda

Syuji Mori

Takasi Sekiba

Toshihiko Kasai

Yoshihiro Kizaki

Haruo Tamada

A D/A converter for receiving a plurality of divisional voltages and converting a digital signal to an analog voltage with the divisional voltages, the D/A converter includes a selection circuit for receiving the divisional voltages and the digital signal to select one of the divisional voltages. The selection circuit includes a plurality of first switch circuits that are selectively activated in response to the digital signal to select one of the divisional voltages, with each of the first switch circuits being provided with a logic switch function and having an ON resistance when activated, and at least an activated one of the first switch circuits further dividing the selected one of the divisional voltages with the ON resistance. The plurality of switch circuits includes at least one voltage dividing switch circuit used to further divide the selected one of the divisional voltages.

D/A converter

A driver IC for a display that includes a first D/A converter with a 1selection circuit that receives 1image signals and supplies a selected positive divisional voltage to a 1operational amplifier, which supplies a positive pixel voltage by amplifying the selected positive divisional voltage; a 2D/A converter with a 2selection circuit that receives 2image signals and supplies a selected negative divisional voltage to a 2operational amplifier, which supplies a negative pixel voltage by amplifying the selected negative divisional voltage; and a polarity switching switch with 1and 2switches connecting the 1and 2D/A converters respectively, the polarity switching switch being switched to supply each of output terminals corresponding to the 1and 2image signals alternately with the positive and negative pixel voltages every horizontal scan period by activating/inactivating the 1and 2switches in a complementary manner.

Driver IC for display and display including same

A drive circuit of a display that decreases the number of gates in a selection circuit to reduce chip area. The drive circuit includes a first voltage dividing circuit for generating a plurality of divisional voltages by dividing a predetermined reference voltage. A selection circuit receives a selection signal and selects one of the divisional voltages. The selection circuit includes a plurality of first switch circuits selectively activated in response to the selection signal to select one of the divisional voltages. Each of the first switch circuits is provided with a logic switch function and has an ON resistance when activated. An activated one of the first switch circuits generates the pixel voltage by further dividing the selected one of the divisional voltages.

Method for driving display and drive circuit for display

A bias circuit generates a first voltage at a first node. A second current source generates, according to the first voltage, a power supply current to be supplied to an internal circuit including transistors. A correcting transistor in a correcting circuit supplies the first node with a correcting current generated according to a constant voltage. Because of this, the first voltage is adjusted according to the correcting current. Therefore, the operating speed of the internal circuit is prevented from changing, being dependent on the variation of the threshold voltage and temperature variation of a transistor. As a result, the yield can be improved, independently of the variation of the threshold voltage among semiconductor integrated circuit chips, which occurs in a fabrication process. Further, temperature dependency of the operating speed of the internal circuit can be reduced, which can improve the yield of the semiconductor integrated circuit.

Semiconductor integrated circuit

The present invention provides a data driver on which an operation test can be easily and reliably conducted at the stage of manufacture and for which the testing time can be reduced and a display utilizing the same. A select switch portionis provided for electrically connecting and disconnecting a ladder resistor portionand selector portions. At the ends of wiring of grayscale voltage lines lthrough lopposite to the ladder resistor portion, there is provided a state setting circuitwhich sets each of the grayscale lines lthrough lat a 'High' level or a 'Low' level or which sets the ends of the grayscale voltage lines lthrough lin a high impedance state. The state setting circuitis further connected to a testing control portionincorporating a shift register which operates in synchronism with a test clock TST-CLK.

Data driver and display utilizing the same

In the LCD panel driving circuit, the voltage of first and second buffer amplifiers is supplied to first output pad, the voltage of second and third buffer amplifiers is supplied to second output pad, and voltage of third and fourth buffer amplifiers is supplied to third output pad. Thus, data-line selection switches and output-polarity selection switches are switched in such a way that the voltage supplied to any adjacent output pads is always supplied from adjacent buffer amplifiers.

Driving circuit for supplying tone voltages to liquid crystal display panel

A semiconductor device including a plurality of chip units each defined by a side wall and arranged in a state such that a side wall of a chip unit abuts a corresponding side wall of an adjacent chip unit, and an interconnection structure for interconnecting a plurality of terminals of a side wall of a chip unit to corresponding terminals of a side wall of an adjacent chip unit that abuts the chip unit at the respective side walls.

Multi-chip semiconductor chip module

A differential amplifier, which is associated with a digital-to-analog converter and a register and serves as an element of an analog-to-digital converter, having the offset input voltage characteristic determined by selecting, for example, the ratio of the emitter areas of a first pair of transistors so that no offset characteristic is required for the digital-to-analog converter associated with the differential amplifier. The offset input voltage can also be determined by selecting the ratio of the emitter areas of a second pair of transistors each one of the second pair of transistors connected to a different one of the first transistors and each one of the second pair of transistors having a current source of the same magnitude. The offset characteristic can also be determined by selecting unequal magnitudes of the current sources connected to the second pair of transistors when the ratio of the second pair of transistor emitter areas are equal. The offset characteristic can also be selected by selecting both the second pair of transistors emitter areas ratios and the second transistor current source magnitudes as not equal or by selecting any combination of the above current magnitudes or emitter area ratios.

Analog-to-digital converter

A diffused resistor for an integrated circuit comprising two resistor portions. Each of the resistor portions comprises a semiconductor substrate of a first conductivity type, an isolated epitaxial region of a second conductivity type, a diffused region (i.e. a resistance layer) of the first conductivity type, a contacting region of the second conductivity type and terminals. An end portion of the resistance layer in one of the resistor portions is connected to one of the ends of the resistance layer in the other resistor portion so that these resistance layers combine to form a resistor. In the other resistor portion the other end portion of the resistance layer is connected to the contacting region. Depletion layers generated in the resistor portions vary so as to maintain the resistance of the diffused resistor constant.

Growing community of inventors

Kasugai, Japan

Osamu Kudo