Lapis Semiconductor Co., Ltd.

Oki Semiconductor Co., Ltd.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Oki Electric Industry Co., Ltd.

Osamu Koike

Yutaka Kadogawa

A semiconductor device includes a semiconductor substrate, active elements, first insulating film, an electrode pad, and a Through Silicon VIA electrode. The semiconductor substrate has an obverse surface and a reverse surface. The active elements define an element-absence area free of any of the active elements. The element-absence area includes a second insulating film, a ring-shaped dummy portion, and island-shaped dummy portions. The ring-shaped dummy portion and the island-shaped dummy portions are made of the same material as the semiconductor substrate. The ring-shaped dummy portion and the island-shaped dummy portions have top surfaces coplanar with a top surface of the second insulating film. The Through Silicon VIA electrode penetrates between an inner edge and an outer edge of the ring-shaped dummy portion from the reverse surface to the obverse surface. Some island-shaped dummy portions are disposed inside of the inner edge of the ring-shaped dummy portion.

Method for manufacturing a semiconductor device having a dummy section

There is provided a semiconductor device comprising a semiconductor substrate having an active area in which a plurality of active elements are formed, and a non-active area excepting the active area; at least one electrode pad electrically connected to any of the active elements. At least one Through Silicon VIA electrode is formed, being electrically connected to the electrode pad by way of the non-active area. The non-active area has an insulating region obtained by forming an insulating film on the semiconductor substrate, and a dummy section obtained by leaving a base material of the semiconductor substrate in the insulating region. The dummy section is provided in a position where an outer edge of the Through Silicon VIA electrode does not intersect with the boundary between the insulating region and the dummy section.

A device with pillar-shaped components, includes a substrate; a wiring layer disposed on the substrate; and pillar-shaped components disposed on any of the substrate and the wiring layer, each of the pillar-shaped components having a bottom part connected to the substrate and/or the wiring layer, a top part opposed to the bottom part, and a lateral face part extending from the bottom part and connected to the top part; wherein each of the pillar-shaped components includes a first pillar-shaped part formed by plating, a second pillar-shaped part formed on the first pillar-shaped part by plating, and a ring-like projection part formed on the lateral face part to project outward and extend in a circumferential direction, and to be in a position higher than a joint position between the first pillar-shaped part and the second pillar-shaped part.

Device with pillar-shaped components

Semiconductor device having a dummy portion, method for manufacturing the semiconductor device, method for manufacturing a semiconductor package having the semiconductor device

A method of fabricating a semiconductor device includes: forming a semiconductor chip portion having an electrode on a main surface of a wafer; forming a first resist pattern having a first opening on the electrode; filling the first opening with a first electrically conductive material, thereby forming an electrically conductive post; removing the first resist pattern after said forming of the electrically conductive post; forming an interlayer dielectric film having a second opening positioned on the electrically conductive post; and forming an electrically conductive redistribution layer extending from an upper surface of the electrically conductive post over an upper surface of the interlayer dielectric film.

Method of fabricating a conductive post on an electrode

An insulator layer is formed on a part of semiconductor substrate to form an isolation layer that insulates and separates active elements from each other in the first region, and to form a dummy portion which is composed of a base material of the semiconductor substrate exposed in the insulator layer in a second region. Active elements are formed in the first region. A silicide layer is formed on the first and second regions excluding at least a portion in which the TSV electrode should be formed. At least one TSV hole extending from a reverse surface side of the semiconductor substrate to an electrode pad via the second region is formed. A conductive film is formed on the inner wall of the TSV hole to form a TSV electrode electrically connected to the electrode pad.

Method for manufacturing semiconductor device

A dummy oxide film having a film thickness that is the same as that of a gate oxide film of a high voltage transistor is formed on a gate electrode of a transistor, and the dummy oxide film and the gate oxide film formed on a substrate surface are removed at the same time during etching for spacer formation. Thus, it becomes possible to stably form a spacer width that sufficiently satisfies device characteristics when manufacturing a semiconductor device where a low voltage transistor and a high voltage transistor are formed on the same semiconductor substrate.

Method of manufacturing semiconductor device

A semiconductor device includes a semiconductor substrate, a gate electrode formed over the semiconductor substrate and a first interlevel insulating layer which is formed over the semiconductor substrate and has first and second contact holes defined by the first interlevel insulating layer. The semiconductor device also includes a first wiring pattern formed in the first contact hole and on the first interlevel insulating layer, a protection layer covering the first wiring pattern and a second interlevel insulating layer which is formed over the first interlevel insulating layer and has a third contact hole defined by the second interlevel insulating layer. The semiconductor device further includes the third contact hole being located on the second contact hole and a second wiring pattern formed in the second and third contact holes and on the second interlevel insulating layer.

Growing community of inventors

Yokohama, Japan

Osamu Koike