Mitsubishi Denki Kabushiki Kaisha

Osamu Kitade

Tetsushi Hoshita

Yutaka Ikeda

Takahiro Komatsu

Hiroshi Itou

The VBL variable circuit is provided with a VBL generating circuit, a test mode judging circuit, a large pump and a small pump, and makes a voltage for precharging a bit line variable. Thus, a defective bit line having little margin with respect to a bit line precharging voltage of a high level or a low level can be detected.

Semiconductor integrated circuit with variable bit line precharging voltage

A reference potential is generated according to a potential Viconst output from a constant current control circuit, and an internal power supply potential is generated based on the reference potential. Fuse elements are provided in the constant current control circuit. Since the resistance value of a resistance circuit can be adjusted, an internal power supply potential can be adjusted in a wider range than that in a conventional circuit. Reduction in yield can be prevented in the case where a threshold voltage or the like is varied.

Semiconductor device capable of adjusting an internal power supply potential in a wide range

A semiconductor storage device having a line-to-line burn-in function of main word lines, applying a stress voltage between the main word lines in a wafer burn-in state. In a wafer burn-in state, by a control circuit means, main word lines are divided to odd-numbered lines and even-numbered lines to be connected to an odd-numbered pad and an even-numbered pad respectively, and a stress voltage is applied directly between the odd-numbered pad and the even-numbered pad. By a row decoder being capable of control in both of an ordinary operation mode and a wafer burn-in operation mode, in a wafer burn-in state, main word lines are divided to odd-numbered lines and even-numbered lines to become selective state, and a stress voltage is applied between main word lines.

Semiconductor storage device having burn-in mode

There is described a semiconductor wafer suitable for efficiently testing a plurality of logic chips formed thereon without damaging input/output sections of the chips. A plurality of chips, a test circuit, and output pads are formed on a semiconductor wafer. A plurality of input pads of the test circuit are connected to terminals corresponding to all the chips by way of a test pattern. The chips are connected to the output pads by means of test patterns. All the chips are subjected to a test (or multi-test) through use of the test circuit and the output pads. The test circuit and the output pads are provided in the peripheral area of the semiconductor wafer.

Semiconductor wafer having a multi-test circuit, and method for manufacturing a semiconductor device including multi-test process

In an REFS generation circuit included in a self refresh circuit of a DRAM, first to fifth N channel MOS transistors are connected in parallel with first to fifth fuses, and first to fifth P channel MOS transistors are connected in series with the first to fifth fuses. If the first to third and fifth fuses are blown to select a fourth clock signal and then the refresh performance is lowered, a third clock signal, for example, having a frequency shorter than the fourth clock signal is selected by rendering conductive only the third N channel MOS transistor and the third P channel MOS transistor of first to fifth N channel MOS transistors and the first to fifth P channel MOS transistors. Therefore, the refresh cycle can be shortened and a DRAM with a refresh failure can be repaired.

Semiconductor memory device having self refresh mode

In a semiconductor memory device a column decoder outputs column select signals which are in turn transmitted to a memory cell block via a transfer gate which turns on when a signal fed through a WBI pad is placed in the inactive state. Even-numbered column select lines are connected via a transfer gate to an even-numbered CSL pad, and odd-numbered column select lines are connected via the transfer gate to an odd-numbered CSL pad.

Semiconductor memory device capable of manifesting a short-circuit failure associated with column select line

A power supply voltage detecting circuit detects whether or not a power supply voltage Vcc is a predetermined reference voltage level or more. The power supply voltage detecting circuit generates a self-refresh mode instruct signal &phgr;A to apply the same to a refresh timer when the power supply voltage detecting circuit determine that the power supply voltage Vcc is a predetermined voltage value or less. The refresh timer carries out a clocking operation in response to the self-refresh mode instruct signal &phgr;A to generate a self-refresh request signal &phgr;srf at a predetermined time interval. A semiconductor memory device is implemented which can carry out the self-refresh mode easily without requiring a complicated timing condition of external signals.

Dynamic type semiconductor memory device operable in self refresh operation mode and self refresh method thereof

A /POR circuit which can detect a power-on of a power supply voltage without fail even in a case where a potential of the power supply rises gently and which produces a /POR signal having a waveform sufficient for initializing internal circuits, as well as a semiconductor device having the /POR circuit. In a power-on reset circuit, a first line potential monitoring circuit and a second line potential monitoring circuit detect a line potential, and there is provided in a /POR signal waveform generation circuit a setting circuit which outputs a pulse signal in response to the results of such detection and operates in response to the pulse signal. Even when the potential of a power-on reset signal rises gently at power-on, the power-on reset signal can be brought to an activation potential without fail, thereby initializing internal circuits.

Power-on reset circuit, and semiconductor device

A semiconductor integrated circuit device includes an operating mode setting circuit for determining an operating mode. Operating mode setting circuit includes an operating mode control circuit and an operating mode alteration circuit. Operating mode control circuit generates an operating mode setting signal depending on wire bonding provided to external input pads. Operating mode alteration circuit includes fuse input pads, electric fuses, and an operating mode inverting circuit. Operating mode inverting circuit inverts an operating mode setting signal once determined by blowing each of electric fuses.

Semiconductor integrated circuit device capable of altering an operating mode by an electrical input applied from outside product package

A semiconductor integrated circuit comprises a NAND gate which constitutes a previous stage circuit, a reset circuit, a charging circuit, and a capacitor for generating a boost potential. A signal of a node A expressing data and a signal of a node B expressing permission of outputting data are not only input to the NAND gate, but also to the reset circuit, and the output of the reset circuit is not only input to the charging circuit but also to the NAND gate; therefore, the previous stage circuit and the reset circuit are interlinked with the output signals. In the result, even in a case where noise is generated in the node A, it is possible to obtain a sufficient boost potential generated in the capacitor.

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Hyogo, Japan

Osamu Kitade