Mitsubishi Heavy Industries Limited

Japan Aerospace Exploration Agency

Osamu Kawasaki

Daisuke Kobayashi

Daisuke Matsuura

Kazuyuki Hirose

Takanori Narita

Masahiro Kato

Shigeru Ishii

Yoshiharu Mori

Masaki Kusano

Yuya Kakehashi

Taichi Ito

The purpose of the invention is to compensate for the radiation tolerance of a semiconductor memory. An apparatus () for compensating for radiation tolerance comprises: a voltage value acquisition unit () that acquires a data retention voltage value that is a maximum voltage value at which data is inverted when a power supply voltage of a semiconductor memory having a latch circuit is lowered; a correction value determination unit () that determines a voltage correction value on the basis of a difference between the data retention voltage value and a reference voltage value; and a voltage adjustment unit () that adjusts at least one among the power supply voltage and a substrate bias voltage by using the voltage correction value. The reference voltage value is set to be equal to or lower than the data retention voltage value that satisfies a required radiation tolerance.

Apparatus for compensating for radiation resistance of semiconductor memory, method therefor, and electronic circuit

A semiconductor device includes first to N-th PLL circuits configured to operate in synchronization with a common reference clock signal to output first to N-th clock signals, respectively; a majority circuit that performs a majority operation on the first to N-th clock signals to generate a majority clock signal; and a filter circuit to which the majority clock signal is provided, the filter circuit operating as a low-pass filter to output an output clock signal. N is an odd number of three or more.

Semiconductor devices

An operation adjustment method of an SOI device comprises steps of: (a) obtaining a drain current-substrate bias voltage characteristic of an NMOS transistor for a source-gate voltage of 0V; (b) obtaining a lowest substrate bias voltage which turns on the NMOS transistor from the drain current-substrate bias voltage characteristic; (c) determining an upper limit of a substrate bias voltage of a PMOS transistor as a voltage obtained by subtracting a built-in potential of a pn junction from the lowest substrate bias voltage; and (d) determining the substrate bias voltage of the PMOS transistor as a positive voltage lower than the upper limit. Reduction in the power consumption and maintenance of the radiation tolerance are both achieved for the SOI device.

Semiconductor device

Growing community of inventors

Tokyo, Japan

Osamu Kawasaki