Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Other

Hitachi Ulsi Engineering Corp.

Osamu Kasahara

Hiromichi Enami

Tsuyoshi Tamaru

Hidetsugu Ogishi

Nobuo Owada

Hiroyuki Akimori

Sinichi Suzuki

Hideo Aoki

Isamu Asano

Yoshinao Kawasaki

Masakazu Sagawa

Osamu Tsuchiya

Toru Kaga

Fumio Ootsuka

Kazuyoshi Torii

Mitsuaki Horiuchi

Jun Sugiura

Makoto Ogasawara

Keisuke Funatsu

Masatoshi Tsuneoka

Takayoshi Kogano

Seiichirou Shirai

Atsushi Wakahara

Nobuhiro Otsuka

Yoshihiro Ikeda

Tomotsugu Shimmyo

Tunehiko Tubone

Ken Tsugane

Yoshitaka Tadaki

Shigeru Kobayashi

Hiroko Kaneko

Hiroyuki Uchiyama

Yutaka Kobayashi

Masayuki Kojima

Hisashi Nakamura

Kazuo Nojiri

Toshihiro Sekiguchi

Atsuyoshi Koike

Jun Murata

Hiroyuki Miyazawa

Atsushi Ogishima

Michimasa Funabashi

Toshio Maeda

Masaki Nagao

Yasuo Kiguchi

Kazuya Kadota

Masato Sadaoka

Tadashi Chikahara

Masao Sakata

Masakazu Ishino

Katsuo Abe

Susumu Tsuzuku

Eisuke Nishitani

Hiroki Nezu

Satoshi Yamamoto

Takashi Hashimoto

Toshiyuki Mine

Hirotaka Nishizawa

Takeo Shiba

Yoichi Tamaki

Yuzuru Ohji

Tohru Kobayashi

Tsuneaki Kamei

Takahiro Kumauchi

Takashi Uchino

Mikinori Kawaji

Hideaki Shimamura

Takahisa Nitta

Shunji Sasabe

Kunihiro Yagi

Seiichiro Azuma

Takeshi Oyamada

Kazuaki Ootoshi

Masataka Miyama

Shuji Kawata

Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.

Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING A FIRST WIRING STRIP EXPOSED THROUGH A CONNECTING HOLE, A TRANSITION-METAL FILM IN THE CONNECTING HOLE AND AN ALUMINUM WIRING STRIP THEREOVER, AND A TRANSITION-METAL NITRIDE FILM BETWEEN THE ALUMINUM WIRING STRIP AND THE TRANSITION-METAL FILM

Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions. The disclosed process includes forming insulating films over wiring lines including uppermost wiring lines, the uppermost wiring lines having gaps between adjacent uppermost wiring lines. The insulating films include forming a silicon oxide film over the wiring lines and in the gaps between adjacent uppermost wiring lines, and forming a silicon nitride film over the silicon oxide film, the silicon nitride film being formed by plasma chemical vapor deposition. The silicon oxide film is formed to have a thickness of at least one-half of the gap between adjacent uppermost wiring lines, with the silicon nitride film being thicker than the silicon oxide film.

Semiconductor integrated circuit device, process for fabricating the

A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.

Semiconductor integrated circuit, method of fabricating the same and

Method of forming teos oxide and silicon nitride passivation layer on

A method of manufacturing an improved bipolar transistor or BiCMOS having a phosphorus-doped polysilicon emitter electrode is disclosed. The method comprises forming an emitter electrode wherein a phosphorus-doped amorphous silicon film is deposited at temperature not higher than 540.degree. C. and then subjected to low temperature annealing treatment at a temperature of 600.degree. C. to 750.degree. C., under which the amorphous silicon is converted to a polysilicon and the phosphorus present in the amorphous silicon film is diffused into a base region to form an emitter region, followed by high temperature/short time annealing treatment at a temperature of 900.degree. C. to 950.degree. C. so that an activation rate of an impurity in a boron-doped polysilicon base electrode or source-drain regions of MOS.cndot.FET is improved.

Method of manufacturing a BIMIS

Semiconductor integrated circuit device process for fabricating the same

The present invention relates to a method for filling small via holes provided to insulating film on a wafer to expose parts of the underlayer of the wafer by metal by means of CVD, and an apparatus therefor. The gist of the present invention lies in that, before CVD is conducted, a surface cleaning treatment of small via hole bottom underlayer surface and a stabilization treatment of insulating film surface activated thereby are carried out successively or simultaneously and optionally an anti-corrosive treatment is applied to underlayer surface, and then the CVD treatment is conducted without exposing the underlayer metal subjected to above treatments to the air. The present invention provides an effect of enabling via filling by metal which shows good selectivity and gives a low interfacial resistance between underlayer metal and filled metal.

Process for forming multilayer wiring

There is provided a semiconductor integrated circuit device having bipolar transistors each composed of an emitter region, base region, and collector region arranged vertically on a semiconductor substrate, said collector region having a plane figure, with the square corners thereof cut off. To be concrete, the buried collector region having a high concentration of impurity has its square corners cut off and the base region formed on the major surface of the epitaxial layer formed on said buried collector region has also its square corners cut off. The bipolar transistor having such a plane figure has a reduced parasitic capacity and an increased operating speed. A manufacturing method is also provided capable of producing a highly reliable groove isolation structure with a low dielectric constant.

Semiconductor integrated circuit device having an improved vertical

Growing community of inventors

Hinode-machi, Japan

Osamu Kasahara