Nec Corporation

Nippon Electric Co., Ltd.

Osamu Ichiyoshi

Akio Kuramoto

Kazuo Kosukegawa

Toshinobu Yamane

In a communication system for carrying out satellite communication through a satellite among users, a satellite communication center is located in a terrestrial network, such as an internet, and has a program table accessible through the terrestrial network and representative of a time schedule of each program to be broadcast through the satellite. The program table can be reserved to broadcast contents by a sender through the internet when an empty time zone is left on the program table. When the reservation is accepted, the contents are sent from the sender through the internet to the satellite communication center and are broadcast at a reserved time through the satellite to other users in accordance with the program table. The contents may be stored in advance in an information storage of the satellite communication center once before they are broadcast or be directly broadcast to the satellite at the reserved time.

Communication system and method capable of broadcasting by using terrestrial and satellite communication networks

Connected to a satellite earth station for transmitting a broadcast signal to a communication satellite, a data (distribution) center publishes contents of stored information on a home page (HP) of the Internet to submit retrieval of users. When each user determines date to be gotten by retrieving on HP, the user transmits a request signal to the date center via a ground Internet or the communication satellite. Responsive to the request signal, the date center returns a reservation signal including a group address and a distribution scheduled time instant to a request source via the communication satellite. A user's terminal receives date with the group address at a reserved time instant, deciphers the date using a key given from the date center separately, and stores deciphered date in a memory thereof.

Satellite communications data distribution system capable of providing a lot of data in response to a user's request

A spreading code setting circuit generates N vectors, as spreading codes, which are +1 or &#x2212;1 polarity and are unique to users. A multiplier multiplies the nth data and the nth spreading code corresponding thereto for the spread modulation. An FDM combining circuit modulates N pieces of data according to the FDM method. A FDM separating circuit demodulates received signals according to the FDM method. An inverse spreading code setting circuit generates N vectors, as inverse spreading codes, which are +1 or &#x2212;1 polarity and are unique to users at the transmission side. A multiplier multiplies the nth data and the nth inverse spreading code corresponding thereto for inverse spread modulation.

FDM-CDMA transmitting method, FDM-CDMA receiving method, FDM-CDMA transmitting device and FDM-CDMA receiving device

A variable-bandwidth frequency-division multiplex communication system which needs no interpolation circuits, but uses switch element of simple structure. The system includes a signal combining circuit which has N A/D converters associated respectively with independent information signals to be transmitted, a complex local oscillator for generating complex signals each having a frequency k.DELTA.f (1.ltoreq.k.ltoreq.N-1), .DELTA.f being the channel frequency interval, N complex multipliers for multiplying the outputs of the A/D converters by the respective complex signals, and producing N output signals, a circuit for effecting an inverse Fourier transform of N points, an N.times.N switch circuit connected between the outputs of the complex multipliers and input terminals of the inverse Fourier transform circuit, N digital subfilters connected respectively to the outputs of the inverse Fourier transform circuit, N delay units connected respectively to outputs of the digital subfilters, and an adder for adding output signals from the delay units and outputting a sum signal.

Variable-bandwidth frequency division multiplex communication system

A radio communication device includes a transmission carrier generating circuit, a reception intermediate-frequency local signal generating circuit), a transmission radio-frequency local signal generating circuit and a reception radio-frequency local signal generating circuit, each of which is in the form of a frequency synthesizer. The radio communication device further includes a channel connection signal control circuit which cooperatively controls the transmission carrier generating circuit and the transmission radio-frequency local signal generating circuit and cooperatively controls the reception intermediate-frequency local signal generating circuit and the reception radio-frequency local signal generating circuit.

Radio Communication device capable of setting a frequency channel with a

A TDMA timing control method and apparatus for use in a TDMA satellite communication network synchronizes land earth stations in a global beam system and even in a multi beam system having generally no return channel. A land earth station of the satellite network generates a transmission timing thereof on the basis of its own time base and detects a receiving time of a signal from another land earth station. Times of the land earth stations are synchronized by exchanging the information of their own transmission timing and the receiving times of the signals with other land earth stations through control bursts, calculating time errors of their own time bases by solving simultaneous equations including time errors of the time bases of the other land earth station and propagation times to the satellite as unknown quantities and correcting the times of the time bases on the basis of the time errors.

Method and system for controlling TDMA timing in satellite communication

A radio communication system comprises a plurality of personal terminals and a base station, the personal terminal being equipped with a non-directional antenna or a directional antenna directed to the base station, which transmits and receives a signal at an identical frequency, the base station, which establishes a communication path between the personal terminals by relaying of the signals, comprising a non-directional transmitting antenna and a receiving antenna located in such a positional relationship as to minimize the amounts of the signals coupled at the respective antennas, and feeds the received signal received by the receiving antenna to the transmitting antenna while cancelling a leakage signal from the transmitting antenna which is contained in the received signal, by using a reference signal set on a given frequency channel which may be modulated with a broadcast signal.

Radio communication system

In a high-power transmitter, an input complex signal is multiplied in a complex multiplier by control signals. The output complex signal from the multiplier is converted to a high frequency signal and amplified by a power amplifier for transmission. The amplitude of the input complex signal is detected to access a memory where amplitude and phase correction values are stored. During a read mode of the memory, a set of amplitude and phase correction values is specified by the detected amplitude and supplied to the complex amplifier as the control signals. During a write mode of the memory, a set of amplitude and phase correction values is specified by a delayed version of the detected amplitude and rewritten with a set of new amplitude and phase correction values. The amplified high frequency signal is down-converted to a low frequency complex signal. The nonlinearity of the power amplifier is determined from a delayed version of the input complex signal and the down-converted complex signal and the new amplitude and phase correction values are produced from the detected nonlinearity and delayed versions of the amplitude and phase correction values which were supplied to the complex multiplier. At intervals, the memory is switched from the read mode to the write mode for updating its contents.

High-power linear amplification using periodically updated amplitude and

To establish radio channels according to a DAMA scheme, FDM radio channels are divided into channel groups, each containing a predetermined number of neighboring channels. The base station includes group modems for FDM modem processing, on a basis of each channel group, into uplink baseband signals uplink radio signals received from source stations in uplink channel groups and downlink baseband signals into downlink radio signals sent to destination stations in downlink channel groups and a switching unit for switching the baseband signals from the uplink channel groups into the downlink channel groups according to the destination stations. Each terminal station includes a group modem for FDM modem processing en-bloc downlink channel group radio signals into downlink terminal baseband signals and uplink terminal baseband signals into uplink channel group radio signals and baseband processors for processing the downlink terminal baseband signals for supply to the communication terminals according to the neighboring channels of the downlink channel group and uplink baseband signals of the communication terminals into the uplink terminal baseband signals according to the neighboring channels of the uplink channel group.

Area radio communication with radio channels divided into channel groups

A first clock signal of fl in frequency is converted into a second clock signal having a frequency of f2=(n/m) f1. The first clock signal is converted by a tank circuit (12) and a converter (13) into an R-bit first phase signal (.theta.1) indicating the phase of the first clock signal. The first phase signal is multiplied by n (mod 2.sup.R) by a multiplier to provide a second phase signal (.theta.3). The second phase signal is supplied to a digital phase-locked loop (PLL) (3) comprising a subtractor (15), a low-pass filter (LPF) (16), a numerically controlled oscillator (NCO) (17) and a multiplier (18). The multiplier in the digital PLL (3) multiplies a third phase signal by m (mod 2.sup.R), indicating the phase of a second clock signal which is the output of the NCO (17), to generate a fourth phase signal. The subtractor (15) generates a signal representing the phase error between the second and fourth phase signals. This phase error signal is filtered by the LPF (16) to control the oscillating phase of the NCO (17). A clock generating circuit generates the second clock signal, on the basis of the third phase signal.

Rate conversion apparatus

A frequency synthesizer is composed of a reference oscillator, the first and the second integrators, a binary adder, a low pass filter and VCO forming a Phase Locked Loop (PLL). The first integrator, driven by the timing of a reference oscillator, integrates an externally supplied value K and generates the input signal. The second integrator, driven by the output signal of the VCO of the PLL, integrates an externally supplied value L. The binary adder detects the difference between the outputs of the first and the second integrators functioning as a phase comparator. The output of the phase comparator is converted into an analog voltage which is filtered to control the VCO to achieve frequency synthesis by the phase lock function of the loop.

Voltage control oscillator which suppresses phase noise caused by

In a phase divider, a complex signal containing a sequence of samples of real and imaginary values is limited to a unit amplitude and multiplied by a first complex multiplier with a first feedback complex signal, the output the multiplier being fed through a loop filter to a second complex multiplier where the signal is multiplied with a second feedback complex signal. The output of the second multiplier is limited to a unit amplitude, delayed by a sample interval and applied to the second complex multiplier as the second feedback complex signal. The first feedback complex signal is derived by a circuit that raises the frequency the delayed signal by a desired factor.

Phase divider for complex signals

In a phase-locked circuit which is operable in response to an input complex signal to produce an output complex signal, a first complex multiplication is carried out between the input and the output complex signals to obtain a phase difference therebetween which appears as a complex phase difference. The complex phase difference is composed of a real part and an imaginary part which are individually allowed to pass through a low pass filter and to be supplied to a numerically controlled oscillator as a control signal. The control signal includes a frequency component even when the phase-locked circuit is put into an asynchronous state. The low pass filter may be replaced by a digital circuit comprising phase dividers.

Phase-locked circuit capable of being quickly put in a phase-locked state

In an antenna device comprising an antenna block which can electrically control a direction of a radio wave transmitted or received by the antenna device, a phase shift unit is connected to the antenna block to phase shift an external electric signal or an internal electric signal given to or from the antenna device. The phase shift unit has variable and discrete phase shifts switched from one to another in response to a control signal supplied from a controller and supplies a phase shifted external signal to the antenna block or a phase shifted internal signal to an external device. The antenna block comprises a plurality of antenna elements and a plurality of phase shifters which are connected to the antenna elements to send the phase shifted external signal to the respective antenna elements or to send the internal electric signal to the phase shift unit.

Antenna device capable of reducing a phase noise

For processing a multiplied signal into a modified signal in a demodulator circuit, an adder (34) sums up a first, a second, and a third processed signal into a sum signal for use as the modified signal. A first processing circuit (31) processes the multiplied signal into the first processed signal. A second processing circuit (32) processes the multiplied signal into the second processed signal in accordance with a conjugate complex clock and a complex local signal. A third signal processing circuit (33) processes the multiplied signal into the third processed signal in accordance with a complex clock and a conjugate complex local signal. The complex clock signal represents a first complex number. The complex local signal represents a second complex number. The conjugate complex clock signal represents a complex conjugate of the first complex number. The conjugate complex local signal represents a complex conjugate of the second complex number.

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Tokyo, Japan

Osamu Ichiyoshi