Mitsubishi Denki Kabushiki Kaisha

Other

Renesas Technology Corp.

Mitsubishi Electric System Lsi Design Corporation

Osamu Hosotani

Yasushi Onishi

Koichi Kawauchi

Akio Kiji

Naoki Takahashi

Etsuko Ishii

A screen display unit includes a display RAM to which a CPU writes palette codes corresponding to character codes, and a selector for selecting display color data read from one of two color palettes on a character code by character code basis in response to the palette codes read from the display RAM. The selector can select one of the two color palettes on a character code by character code basis, thereby making it possible to carry out display in a greater number colors on the same screen than the number of colors indicatable by the display color codes stored in the display RAM without increasing the capacity of a font data memory.

Screen display unit capable of displaying greater number of colors on the same screen

When a manufacturer or a user desires to adjust a Braun tube, it is required to display a test pattern satisfying setting conditions of display modes on the Braun tube. To set the display modes of the test pattern, a plurality of horizontal synchronizing signals and a vertical synchronizing signal are generated by a timer circuit for each field. Also, display modes (for example, shape, position, size, color and luminance) of a type of characters having the same shape are set in an OSD circuit to set the display modes of the test pattern composed of the characters having the same shape. Thereafter, a composite video signal of the test pattern satisfying the display modes is produced on the basis of the horizontal synchronizing signals and the vertical synchronizing signal in the OSD circuit, and the test pattern is displayed on the Braun tube according to the composite video signal. Accordingly, because the composite video signal of the test pattern satisfying the display modes can be produced without using any private circuit, the video signal producing apparatus can be produced in a small size and at a low cost.

Video signal producing apparatus and video signal producing method

A CPU outputs address data indicating a data storing unit or an OSD-RAM to access the data storing unit or the OSD-RAM, and an OSD logical circuit sometimes accesses the OSD-RAM to display data on an on-screen display. The address data is decoded in an OSD-RAM address decoder, and a decoded signal of &ldquo;0&rdquo; or &ldquo;1&rdquo; is output to an OR gate. Also, a value &ldquo;0&rdquo; normally set in a 1-wait register is output to the OR gate. When the address data indicates the data storing unit, a value &ldquo;0&rdquo; is output from the OR gate to a bus interface unit (BIU), an access mode of the CPU is set to a no-wait access mode corresponding to a shortest cycle, and the CPU accesses the data storing unit at the no-wait access mode. In contrast, when the address data indicates the OSD-RAM, a value &ldquo;1&rdquo; is output from the OR gate to the BIU, an access mode of the CPU is set to a 1-wait access mode corresponding to a double cycle, and the CPU accesses the OSD-RAM in the first half of the double cycle. When the accessing of the OSD logical circuit to the OSD-RAM is performed simultaneously with the accessing of the CPU to the OSD-RAM, the OSD logical circuit accesses the OSD-RAM in the second half of the double cycle. Therefore, software processing efficiency can be improved.

Microcomputer having on-screen display

The OSD includes a plurality of holding circuits for outputting to a mixing circuit pixel data for characters or patterns synchronously with a horizontal synchronization signal, wherein the pixel data for the characters or patterns to be displayed are supplied to the holding circuits by a memory through a plurality of channels, the number of which is equal to the number of the holding circuits, so that a display signal for displaying the pixel data in a plurality of display areas is generated by the mixing circuit.

On screen display

A microcomputer whose ROM program can be altered without the necessity of rebuilding or remaking the ROM, wherein when an address outputted from a CPU to an address bus matches one of the addresses of locations at which the ROM program is to be altered, the ROM is disconnected from a data bus and a jump instruction op code is outputted to the data bus, followed by the start address of an altered contents stored in a RAM or the start address of an instruction for locating among a plurality of altered contents, the start address of the altered content that is substituted for the portion of the program to be altered; then, the CPU reads the jump instruction op code and the start address, the operand of the jump instruction, outputted on the data bus, and executes the jump instruction by which a jump occurs from the ROM program to the altered contents stored in the RAM to execute the altered contents, and control returns to the ROM program after the execution of each altered content, thereby altering the ROM program at a plurality of portions thereof.

Microcomputer having ROM program which can be altered

A screen display circuit, comprising: a register 13 storing data designating a screen whereon a pattern is displayed, and a position of the pattern on the screen; a RAM 4 storing data designating the pattern; first and second buffers 15, 16 which temporarily stores and output addresses of the patterns to be displayed respectively on the first and second screens; a ROM 5 storing a plurality of font data; a switch 17 which connects the ROM 5 alternately to the first buffer 15 and the second buffer 16; and a mixing circuit 22 which composes dot data of the patterns to be displayed on the first and second screens outputted alternately from the ROM 5, whereby the first screen and the second screen, whereon dot patterns are respectively displayed, are composed and displayed on a display apparatus. As a result, hardwares can be reduced and a manufacturing cost can be reduced.

Screen display circuit

A screen display device is provided with address decoder 15, address generator 16, address translation circuit 17, data buffer 18 and data translation circuit 19 and is designed to reduce a rewrite operation time by rewriting data with a plurality of addresses of display memory 4 to the same data by the instruction of CPU 1. Further, it is possible to perform rewriting of the display characters, i.e. rewriting of display memory data efficiently and at a high speed.

Screen display device

A screen display device which displays characters and patterns on a TV screen or other screen having a separate blanking signal output controlled by set data for each character in the display memory. Different displays can be shown on several different screens by controlling a color signal which combines the set data for each character and the set data for each screen.

An address control device changes the internal address corresponding to the address at which an error occurred to a new address if an error is detected in a data word during a read from a main memory device. The address control device specifies a different memory area during subsequent data writes and does not use the memory area in which the previous error occurred. Moreover, if the error detection device detects an error while a data word is read from the main memory device, a correction device corrects the data word.

Growing community of inventors

Hyogo, Japan

Osamu Hosotani