Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Osamu Hirabayashi

Nobuaki Otsuka

Keiichi Kushida

Yasuhisa Takeyama

Atsushi Kawasumi

Akira Katayama

Takahiko Sasaki

Hiroyuki Ohtake

Yasushi Kameda

Yuki Fujimura

Hiroshi Hatada

A sense timing generation circuit of an embodiment is a sense timing generation circuit that outputs, from an output terminal, a sense amplifier enable signal for bringing a sense amplifier into an enable state, based on a clock signal input from an input terminal, and includes a delay circuit unit that has a temperature characteristics by which a delay amount decreases in accordance with a temperature rise, includes a plurality of types of a plurality of delay circuits being different in the temperature characteristics, and delays the clock signal and outputs the clock signal as the sense amplifier enable signal, and a connection switch unit that switches a connection state of a plurality of delay circuits in the delay circuit unit from the input terminal to the output terminal.

Sense timing generation circuit and semiconductor memory device

A reference voltage generating circuit according to an embodiment includes: an original reference voltage generating unit that generates an original reference voltage; and a reference voltage correcting unit that decreases the original reference voltage as the temperature rises and outputs the original reference voltage as a reference voltage to a sense amplifier, and thus it is possible to perform highly reliable operation while the influence of the temperature is reduced.

Reference voltage generating circuit and semiconductor memory device

According to an embodiment, a load adjusting circuit adjusts the load of an inverter circuit based on a threshold voltage of a first conductive type transistor provided on the inverter circuit, and a driving force adjusting circuit adjusts the driving force of the inverter circuit based on the threshold voltage of the first conductive type transistor.

Delay circuit and semiconductor memory device

A memory cell of a static random access memory (SRAM) includes a pair of drive transistors, a pair of load transistors, a pair of write-only transfer transistors, a pair of read-only transfer transistors, a pair of read-only drive transistors, and a pair of column selection transistors. The memory cell also includes a word line, a pair of write bit lines, a pair of read bit lines, and a column selection line.

Semiconductor storage device

A semiconductor memory device comprises a memory cell array including a plurality of mutually intersecting word lines and bit lines, and a plurality of memory cells connected at intersections thereof and each having a read port and a write port provided independently; and a plurality of word line drivers operative to drive the word lines. The elements contained in the memory cell have respective sizes in common with the elements contained in the word line driver.

Semiconductor memory device

A semiconductor memory device comprises: a memory cell array including a plurality of word lines, a plurality of bit line pairs containing a first bit line and a second bit line, and a plurality of memory cells; a plurality of replica bit lines formed in the same manner as the first and second bit lines; a write buffer circuit operative to drive the first or second bit line to the ground voltage; a replica write buffer circuit operative to drive the replica bit lines to the ground voltage; and a boot strap circuit operative to drive the first or second bit line currently driven to the ground voltage further to a negative potential at a timing when the potential on the replica bit lines reaches a certain value.

A semiconductor memory device according to an aspect of the invention includes plural writing word lines; first and second writing bit lines that intersect with the writing word lines; and plural memory cells that are provided at portions in which the plural writing word lines and the first and second writing bit lines intersect with each other. In the semiconductor memory device, the memory cell includes a flip-flop circuit that includes first and second nodes of a complementary pair; a first transfer transistor that is connected between the first writing bit line and the first node, a gate of the first transfer transistor being connected to the writing word line; and a second transfer transistor that is connected between the second writing bit line and the second node, a gate of the second transfer transistor being connected to the writing word line. The first and second writing bit lines are in a floating state whenever data is not written in the memory cell.

A semiconductor memory device includes a memory cell array having a plurality of read word lines, a plurality of first and second read bit lines, and a plurality of memory cells arranged in array. The memory cell includes a first and a second cell node in complementary pair, a first drive transistor controlled by the second cell node, and a second drive transistor controlled by the first cell node. The read word line and the first read bit line are connected with each other via the first drive transistor. The read word line and the second read bit line are connected with each other via the second drive transistor.

A semiconductor memory device comprises a logic circuit supplied with a first supply voltage; a cell array supplied with a second supply voltage higher than the first supply voltage and including plural mutually intersecting word lines and bit lines and plural memory cells connected at intersections thereof; and a word line driver operative to drive the word lines. The word line driver includes plural pull-up circuits connected between the supply terminal of the first supply voltage and the drive terminal of the word line and between the supply terminal of the second supply voltage and the drive terminal of the word line, and a pull-down circuit connected between the drive terminal of the word line and the ground terminal, and drives the word line with an intermediate voltage between the first and second supply voltages in accordance with a driving force ratio between the plural pull-up circuits at the time of driving the word line.

Semiconductor memory device having integrated driving word line intermediate voltages by pull-up circuits

A semiconductor device has a memory section including a first and second memory cell storing a data bit and error correcting bit, respectively. An error correcting section outputs a data signal containing an error-corrected data bit, using the error correcting bit and an information signal when the error is corrected. A test section outputs a first determination signal when the memory section is determined to be faulty by checking the data signal based on a program. A counter section counts the number of times by which the information signal is supplied thereto and outputs a second determination signal when the result of counting becomes equal to a reference value. A determining section determines that the memory section is faulty when one of the first and second determination signals is supplied thereto.

Semiconductor device

A semiconductor memory device operates using a first power supply and a second power supply. The device includes a static memory cell which receives the first power supply, a word line which is connected to the memory cell, and a decoder which controls selection/deselection of the word line on the basis of an address signal having a voltage of the second power supply. The decoder includes a level shifter which changes a voltage of the word line to a voltage of the first power supply, and a switching circuit which receives the first power supply and applies a voltage lower than the first power supply to the level shifter in selecting the word line.

A semiconductor memory device includes a memory cell array provided in a cell array area and including a plurality of memory cells, a source potential line which applies a source potential to the memory cells, a switching element group provided in the cell array area adjacent to the memory cell array, the switching element group electrically connecting the source potential line to a ground potential line, when the memory cells are in an operation mode, a first P-type MIS transistor connected between the source potential line and the ground potential line, and fixing the source potential when the memory cells are in the sleep mode, and a bias generation circuit provided in a peripheral circuit area, and supplying a first bias potential to the first MIS transistor, the first MIS transistor being provided in the peripheral circuit area.

A semiconductor memory device includes a memory cell array including memory cells, word lines which select the memory cells, bit lines which transfer data of the memory cells, a sense amplifier circuit which amplifies data transferred to the bit lines, a first dummy cell group including first dummy cells, a dummy word line which selects the first dummy cell group, a dummy bit line to which data of the first dummy cell group is transferred, a generation circuit which generates an activation signal to activate the sense amplifier circuit based on a variation in a potential level of the dummy bit line, and a potential generating circuit which generates a first source potential applied to the first dummy cell group. The first source potential is different from a power supply potential.

A semiconductor memory device includes a first inverter circuit and a second inverter circuit, a first transfer gate which is connected between a first power node of the first inverter circuit and a first bit line, a second transfer gate which is connected between a second power node of the second inverter circuit and a second bit line, a first word line connected to gate terminals of the first transfer gate and the second transfer gate, a first read transistor connected between the first power node and a second word line, a second read transistor connected between the second power node and the second word line, and an application circuit which is connected to the second word line, and applies a read voltage to the second word line in reading data.

A semiconductor device whose operation frequency and power supply voltage are dynamically controlled according to a load subjected to a process to be performed is disclosed. The semiconductor device includes a memory cell array having SRAM cells arranged in an array form, word lines connected to the SRAM cells for respective rows, a row decoder which selects the word lines one by one during normal operation and multi-select word lines which are not adjacent to each other during low-voltage operation, a load circuit which sets the level of the selected word line to potential lower than power supply voltage, and a controller which controls the row decoder and load circuit to selectively control selection of the word lines and the load circuit.

Growing community of inventors

Tokyo, Japan

Osamu Hirabayashi