Yamaha Corporation

Nippon Gakki Seizo Kabushiki Kaisha

Osamu Hanagasaki

Terumoto Nonaka

Tadahiko Hotta

Yasunori Mochida

In a DRAM memory cell built in a semiconductor device, a capacitor is formed on a field oxide film so as not to superpose upon a transistor. An area of the field oxide film can therefore be used efficiently. Since the capacitor can be formed before the transistor is formed, high temperature treatment in forming the capacitor does not give adverse effects on the transistor characteristics. The capacitor dielectric film can be made of material of a high dielectric constant. The capacitor dielectric layer and lower electrode are formed by patterning in succession with the same etching mask. The gate electrode is formed at the same time when the upper capacitor electrode is formed. At the same time when the gate oxide film is formed, an oxide film is formed also on the surface of the capacitor dielectric layer. Pin holes in the dielectric layer are buried by this oxidation. With a reduced number of processes, the additional number of manufacture processes for built-in memory cell in addition to the manufacture processes of logic circuit can be made small. A semiconductor device and its manufacture method are provided which have less load on processes and a small memory cell size.

DRAM capacitor having lower electrode and dielectric layer of same

A method of manufacturing a semiconductor storage device having a plurality of memory cells each having one transistor and one ferroelectric capacitor includes the steps of: forming a transistor; forming a plate line; sequentially laminating three layers including a first conductive film, a ferroelectric layer, and a second conductive layer stacked in this order; and sequentially etching the three layers by using a single etching mask. It is possible to maintain the contact surface between the electrodes and ferroelectric layer of a ferroelectric capacitor clean and the characteristics of the ferroelectric capacitor of the semiconductor storage device can be improved.

Semiconductor memory device with ferroelectric capacitor

In a process according to the present invention, a polysilicon gate electrode and a high resistive polysilicon strip are simultaneously patterned on an active area and on a thick field oxide film, respectively, and the gate electrode and the polysilicon strip are covered with thin silicon oxide films, respectively, then impurities being doped in the active area to form source and drain regions, then the thin silicon oxide film being removed from the gate electrode, then a refractory metal silicide film being formed on the gate electrode, however, the formation of the refractory metal silicide film does not affect the polysilicon strip, because the thin silicon oxide film is left thereon, which results in maintaining the polysilicon strip in the high resistivity and, accordingly, in that the polysilicon strip provides a resistor with a large resistance but occupies a small amount of area.

Process of fabricating semiconductor integrated circuit having

An electrode using Ti or Zr having a highly reactive property but insuring a good and stable electric contact with a silicon semiconductor device surrounded by an oxygen atom-containing insulating film is realized with simplified and reduced manufacturing steps at a reduced cost by first revealing a selective surface region of the silicon semiconductor through a window, and then laminating thereon including the selective surface region a first metal layer of Ti or Zr and then a second metal layer of Mo or W to cover and protect the first metal layer from oxidation, and then etching away the laminated layers leaving that portion corresponding to the selective surface region of the device, and thereafter heating the assembly to form a silicide of the first metal with silicon of the underlying semiconductor. The upper metal layer is covered with a protective insulating layer to avoid oxidation of the upper metal layer. The step of covering with the protective insulating layer should preferably be taken before the heat-treatment for the silicide formation.

Method of manufacturing a multilayer electrode containing silicide for a

A process of fabricating a semiconductor device comprising the steps of forming a dielectric layer overlying a doped semiconductor layer, forming a first insulator layer on the dielectric layer, etching the dielectric layer and the insulator layer to form a bump region comprising coextensively patterned portions of the dielectric and insulator layers, forming a second insulator layer partly on the doped semiconductor layer and partly on the bump region, conformally forming on the second insulator layer an undoped polycrystalline semiconductor layer having a step portion, forming on the polycrystalline semiconductor layer a planarizing layer covering the step portion of the polycrystalline semiconductor layer, etching back the polycrystalline semiconductor layer and the planarizing layer until the second insulator layer has a surface portion exposed over the bump region, etching the first and second insulator layers with the remaining portion of the polycrystalline semiconductor layer used as a mask for forming an opening in part extending to the surface of the dielectric layer and having a marginal groove portion extending to the surface of the doped semiconductor layer, and thereafter forming various desired device regions through and in alignment with this opening.

Process of fabricating semiconductor device involving planarization of a

A reference frequency generator for a tuning apparatus comprising a variable frequency divider which frequency divides a source signal in accordance with frequency division data stored in one or more ROM's. The frequency division data comprises note data for specifying frequencies of respective notes in one octave of a musical scale, pitch deviation data for specifying pitch deviation of the respective notes in one octave with respect to the frequencies specified by said note data and tuning curve data for specifying tuning characeristics covering several octaves, so that the generator generates reference frequency signals representing various pitch deviations and tuning characteristics as well as a standard tuning pitch or characteristic.

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Hamamatsu, Japan

Osamu Hanagasaki