Kabushiki Kaisha Toshiba

Nsk Corporation

Sony Corporation

Osamu Fujii

Takashi Murai

Tsutomu Sato

Hiroshi Ohno

Ichiro Mizushima

Takashi Yamada

Hajime Nagano

Yoshinori Honguh

Masataka Shiratsuchi

Shinichi Tsunashima

Hisato Oyamatsu

Tomoya Sanuki

Tetsuo Watanabe

Takeshi Shibata

Shinji Miyano

Hiroaki Yamada

Koji Ueda

Yoshihiro Minami

Shinichi Nitta

Yoshimasa Kawase

Katsuhiro Konno

Keijiro Yamaguchi

Yoshiki Nakamura

Kenji Kotaki

Takayuki Matsushita

Kaoru Hiyama

Michitsugu Mori

The contact portion of the end face of a conical roller, which is a portion to be slidingly contacted with a collar portion, is ground such that the outer contour line of the section thereof has a continuously curved line which passes through at least not only the first point but also between the third position and fourth position.

Roller bearing

According to one embodiment, an image sensor includes an image-sensing element region formed by arranging a plurality of image-sensing elements on a semiconductor substrate, and a logic circuit region formed in a region different from the image-sensing element region on the substrate and including a plurality of gate patterns. Further, dummy gate patterns are formed with a constant pitch on the image-sensing element region.

Image sensor and manufacturing method thereof

According to one embodiment, a solid-state image sensing device manufacturing method includes forming a photoelectric converting element, a diffusion layer included in a floating diffusion, and a read transistor, in a photoelectric converting element formation region of a semiconductor substrate, a floating diffusion formation region, and a read transistor formation region located between the photoelectric converting element formation region and the floating diffusion formation region, respectively, and forming a semiconductor layer including a impurity on the diffusion layer on the semiconductor substrate.

Solid-state image sensing device manufacturing method and solid-state image sensing device

According to one embodiment, an image sensor includes an image-sensing element region formed by arranging a plurality of image-sensing elements on a semiconductor substrate and element isolation portions formed to isolate the image-sensing elements, and a logic circuit region formed in a region different from the image-sensing element region on the substrate and including a plurality of gate patterns. Further, dummy element isolation portions are arranged with a constant pitch in the boundary region between the image-sensing element region and the logic circuit region.

Image sensor that includes a boundary region formed between a logic circuit region and an image-sensing element region and manufacturing method thereof

Image sensor including an image-sensing element region and logic circuit region and manufacturing method thereof

A measuring device measures a gate length of a plurality of gate electrodes formed on a wafer. A calculation device calculates data of an ion implantation dosage for making uniform a threshold voltage in a wafer surface on the basis of distribution of the gate length in a wafer surface measured by the measuring device. The ion implantation device implants ions into the wafer on the basis of the data of the ion implantation dosage calculated by the calculation device.

Manufacturing system for semiconductor device capable of controlling variation in electrical property of element in wafer surface and method for manufacturing the semiconductor device

Disclosed herein is an electrolytic erosion preventing insulated rolling bearing and a manufacturing method thereof. In one embodiment, the electrolytic erosion preventing insulated rolling bearing includes an insulating coating being a ceramic coating layer including alumina as the main component and 0.01 to 0.2 percent by weight titanium oxide with the alumina having a particle size ranging from 10 to 50 &#x3bc;m and average particle size ranging from 15 to 25 &#x3bc;m.

Electrolytic erosion preventing insulated rolling bearing, manufacturing method thereof, and bearing device

A semiconductor device according to one embodiment includes an element isolation insulating film formed on a substrate, an element region and a dummy pattern region demarcated by the element isolation insulating film on the substrate, a first epitaxial crystal layer formed on the substrate within the element region, and a second epitaxial crystal layer formed on the substrate within the dummy pattern region. The first epitaxial crystal layer is made up of crystals that have a different lattice constant from that of the crystals that constitute the substrate. The second epitaxial crystal layer is made up of the same crystals as the first epitaxial crystal layer. The (111) plane of the substrate that includes any points on the interface between the second epitaxial crystal layer and the substrate is surrounded by the element isolation insulating film in a deeper region than the second epitaxial crystal layer.

Semiconductor device with epitaxial crystal layer embedded within susbstrate of dummy pattern region

A semiconductor device includes a substrate having a first area and a second area adjacent to the first area, a first silicon layer provided on the substrate in the first area, a relaxed layer which is provided on the substrate in the second area and which has a lattice constant greater than a lattice constant of the first silicon layer, and a strained-Si layer which is provided on the relaxed layer and which has a lattice constant substantially equivalent to the lattice constant of the relaxed layer.

Semiconductor device and manufacturing method thereof

A liquid crystal orientation layer contains at least one polymer selected from polyamic acids and polyimides and at least one epoxy compound having a chemical structure represented by the following formula (1) or (2), the X moieties in the formulae containing an alicyclic epoxy group or a glycidyl group represented by the following formula (a) or (b):   with the substituents as defined herein the specification.

Liquid crystal orientation layer and liquid crystal display element

A semiconductor device comprises a semiconductor substrate, a plurality of transistors provided in the semiconductor substrate, and an isolation region for isolating the plurality of transistors to one another, the isolation region being comprised of an isolating insulation film, wherein a crystal structure of at least a part of the isolating insulation film is broken.

Semiconductor device

A semiconductor device includes a first semiconductor region having a buried oxide layer formed therein, a second semiconductor region in which the buried oxide layer does not exist, a trench formed to such a depth as to reach at least the buried oxide layer in a boundary portion between the first and second semiconductor regions, and an isolation insulating layer buried in the trench.

Manufacturing method of partial SOI wafer, semiconductor device using the partial SOI wafer and manufacturing method thereof

A semiconductor device includes first and second semiconductor layers and first and second MOS transistors. The first semiconductor layer is provided on and electrically connected to the semiconductor substrate. The second semiconductor layer is provided near the first semiconductor layer and formed above the semiconductor substrate via one of an insulating film and a cavity. The first and second MOS transistors are respectively provided on the first and second semiconductor layers, and each has a gate electrode arranged parallel to a boundary between the first and second semiconductor layers.

Growing community of inventors

Yokohama, Japan

Osamu Fujii