Intel Corporation

Orna Etzion

Jianhui Li

Yun Yu Wang

Peng Zhang

Jian Ye Chen

Bo Huang

Yu Wang

Sion Berkowits

Yigal Zemach

Alex Skaletsky

Li Jianhui

Gal Moas

Baiming Gao

Harold Theodore Devor

Qi Zhang

Embodiments of the invention disclose a method, apparatus and system of translating a source binary code into a target binary code. The translation according to embodiments of the invention may include determining whether or not a previously translated code block that relates to a source fragment to be currently translated may be reused for execution by a target processor. A reusability status of the previously translated code block may be determined based on a reusability status of a group of previously translated code blocks. In some embodiments, when no previously translated code blocks relating to the currently translated source fragment are found, the source fragment may be translated into a new target code block, which may be executed by the target processor. The new target code block may then be added to a group of previously translated code blocks.

Apparatus, system, and method of dynamic binary translation with translation reuse

Device, system and method for detection and handling of misaligned data access. A method may include, for example, detecting misaligned data access resulting from execution of a code block translated from a first format suitable for a first computing platform to a second format suitable for a second computing platform, and modifying said code block according to said misaligned data access.

Device, system and method for detection and handling of misaligned data access

A binary translation module is to translate a first sequence of instructions associated with a source architecture into a second sequence of instructions associated with a target architecture. The first sequence includes one or more floating point control instructions and the second sequence does not include a floating point control instruction. Results produced by executing the second sequence on a processor that complies with the target architecture are substantially the same as results produced by executing the first sequence on a processor that complies with the source architecture.

Apparatus and methods to avoid floating point control instructions in floating point to integer conversion

A method may translate a set of source instructions into a set of target instructions, execute the set of target instructions, and unmask a denormal input control bit if the set of source instructions uses a denormal input handling mechanism. A method may detect at least one denormal exception of a faulty target instruction by executing the set of target instructions; assign a predetermined value to one or more denormal operands of the faulty target instruction; and execute the faulty target instruction with the predetermined value for the one or more denormal operands. An apparatus, system, and machine-readable medium may perform such methods.

Apparatus, system, and method of dynamic binary translation supporting a denormal input handling mechanism

A method of generating an expected TOS during translation of instructions. The method includes translating a first block of instructions executable in a first processor architecture, into a translated first block of instructions executable in a second processor architecture, wherein the translated first block of instructions operate with a stack of data entry positions. During the translation, an expected Top of Stack (TOS) position in the stack for the first block of code is generated.

Executing a translated block of instructions and branching to correction code when expected top of stack does not match actual top of stack to adjust stack at execution time to continue executing without restarting translating

An arrangement is provided for translating a plurality of scalar single instruction multiple data stream (SIMD) instructions into a plurality of optimized non-scalar SIMD instructions to be executed on a target architecture supporting only parallel SIMID instructions. After receiving a plurality of scalar SIiVLD instructions, translation from the scalar SIMD instructions to non-scalar SIMD instructions is performed. The translation is optimized so that the number of translated non-scalar SIMD instructions is minimized. The translated non-scalar SIIViD instructions are executed on a target architecture that supports only parallel SIMD instructions.

Optimized translation of scalar type SIMD instructions into non-scalar SIMD instructions

A method of monitoring processor resources. To monitor a processor resource, first a set of needed resources is determined at the beginning of a block of code. A test is then performed to determine if the set of needed resources is available at the start of the block of code. An error is signaled if the needed resources are not available at the beginning of the block of code.

Method and apparatus for stack emulation during binary translation

In one embodiment of the invention, a register format of a source register operated on by a source instruction in a source block of code is determined. The register format includes an input instruction format and an output block format of the source block of code. The source block of code runs in a source architecture. The source register has multiple formats and is used as an input of the source instruction. The input instruction format contains format of the source register expected by the source instruction. The output block format contains format of the source register after the source block of code is executed. An instruction format inconsistency is detected between the source register and a target register of a target architecture during a translation phase of a binary translation that translates the source block of code into a target block of code running in the target architecture.

Tracking format of registers having multiple content formats in binary translation

Mapping of exception masks between source and target architectures with different numbers of exception masks enables a binary translator to translate code from the source to the target architecture and to determine an appropriate state for the source architecture if an exception is raised when executing the translated code.

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Haifa, Israel

Orna Etzion