Amazon Technologies, Inc.

Quantum Machines

Q.m Technologies Ltd.

Tel Aviv University

Tel Hashomer Medical Research Infrastructure and Services Ltd.

B.g. Negev Technologies and Applications Ltd.

Ori Weber

Ron Diamant

Michael Baranchik

Nissim Ofek

Itamar Sivan

Yonatan Cohen

Svetlana Kantorovych

Nir Halay

Erez Izenberg

Adiel Sarusi

Lior Ella

Omer Shaked

Yair Sandberg

Uri Abend

Nafea Bshara

Georgy Machulsky

Arnaldo Mayer

Uri Leder

Benzi Denkberg

Eli Konen

Nahum Kiryati

Moshe Hadani

Shlomo Greenberg

Evgeny Paperno

Yossi Rabinowicz

Ron Tsechanski

Erez Manor

Muhannad Ghanem

Guy Osi

Tamar Ben Haim Sembira

Avishai Ziv

Avishai Zvi

In a quantum computer, quantum algorithms are performed by a qubit interacting with a quantum control pulse. This quantum control pulse is an electromagnetic RF signal that is generated at baseband according to an analog waveform. An application circuit digitally generates samples of this analog waveform. These waveform samples are further modified according to post-processing instructions. To avoid processing gaps, the waveform samples and the modification instructions are maintained in buffers that are accessed independently. To maintain coherency, the waveform samples and the modification instructions are read simultaneously by an execution controller.

Buffering the control of a quantum device

Quantum algorithms are performed via a quantum computer, by generating a quantum control pulse in a quantum controller and transmitting the quantum control pulse to a quantum processor. The quantum control pulse interacts with a qubit in the quantum processor. Within the quantum controller, a pulse processor generates a plurality of raw pulses that are modified by a front end hardware module. During the normal operation of the quantum controller, samples of the raw and/or modified pulses may be selected and saved to memory. During a design for validation (DFV) mode, the proper operation of the quantum controller is determined according to a simulation of the quantum controller and the saved samples. The DFV mode may be performed in parallel with normal operation without affecting the resources of the quantum controller.

Quantum controller validation

Methods and systems for classical processing in a quantum controller.

Classical processor for quantum control

A set of quantum controllers are operable to transmit quantum state data to a quantum control switch. The quantum control switch comprises vector processors that operate on the quantum state data from the set of quantum controllers. Each vector processor transmits a result of the operation to a corresponding quantum controller in the set of quantum controllers.

System and method for processing between a plurality of quantum controllers

A pulse generation circuit in a quantum controller operates synchronously with a pulse computation circuit. The pulse generation circuit generates a pulse associated with a quantum element operation. The pulse computation circuit is able to determine characteristics of a signal that is based on the pulse. These characteristics are used by the pulse generation circuit to modify the pulse.

System and method for pulse generation during quantum operations

In a quantum computer, quantum algorithms are performed by a qubit interacting with multiple quantum control pulses. The quantum control pulses are electromagnetic RF signals that are generated digitally at baseband and sent, via asynchronous ports, to DACs that feed an RF upconversion circuit. For synchronization, each asynchronous port is coupled to a multi-tap delay line. The setting of the multi-tap delay line is determined by a function of the port's setup-and-hold time. This function is trained, via machine learning, to be applicable across a variety of ports.

Machine learning for syncing multiple FPGA ports in a quantum system

A channel between quantum controller modules (e.g., pulse processors) is operable to communicate high speed data required for processing qubit states that may be distributed across a quantum computer. The latency of the communication channel is deterministic and controllable according to a system clock domain.

System and method for communication between quantum controller modules

A system comprising a quantum control data exchange circuit that enables a large, variable number of pulse generation circuits to exchange data within the coherence time of a plurality of quantum elements to enable feedback-based quantum control of a large, variable number of quantum elements.

Highly scalable quantum control

Techniques disclosed herein relate to dynamically configurable multi-stage pipeline processing units. In one embodiment, a circuit includes a plurality of processing engines and a plurality of switches. Each of the plurality of processing engines includes an input port and an output port. Each of the plurality of switches comprises two input ports and two output ports. For each processing engine, the input port of the processing engine is electrically coupled to one of the switches, the output port of the processing engine is electrically coupled to another one of the switches, and the input port of the processing engine is electrically coupled to the output port of each of the processing engines by the switches.

Dynamically configurable pipeline

Environmental modification testing with a formal verification is implemented for language-specified hardware designs. A language-specified hardware design may be received. A reference copy of the language-specified hardware design may be created. A formal verification may be performed on both the language-specified hardware design and the reference copy with a same input data. Different environmental assumptions for processing the same input data through the reference copy and the language-specified hardware design may be applied. An output value of the language-specified hardware design may be compared with an output value of the reference copy to determine whether those output values match. Error indications may be provided based on a result of the comparison.

Environmental modification testing for design correctness with formal verification

A compression circuit includes a buffer, a selection circuit, a compare circuit, and a control circuit. The buffer stores uncompressed data. The selection circuit generates a read pointer value to the buffer. The control circuit contains a programmable configuration register. The configuration register stores a depth value for reading uncompressed data from the history buffer. The control circuit generates control signals to the selection circuit to cause the selection circuit to iteratively increment the read pointer value from an initial value to a second value that corresponds to the depth value. Responsive to the second value corresponding to the depth value, the control circuit resets the read pointer value to the initial value. The compare circuit compares input symbols from a data source to uncompressed data from the buffer history to thereby generate output compressed data.

Configurable compression circuit

A configurable sponge function engine. The configurable engine includes a register having bitrate and capacity sections, each having a variable size, where a sum of the bitrate and capacity sizes is fixed. A controller generates a bitrate size indication. A configurable message processor receives an input message from an input bus, receives the size indication, fragments the input message into fragmented blocks of a size specified by the size indication, and converts the blocks to a bus width of the bitrate and capacity sizes. An iterative calculator receives the blocks, performs iterative processing operations on the blocks, and stores a result of each operation in the register overwriting a previous register value. An output adaptor receives a value stored in the register after the block corresponding to the end of the input message is processed and outputs the register value converted to have an output bus width.

Configurable sponge function engine

A computing system includes a network interface, a processor, and a decompression circuit. In response to a compression request from the processor the decompression circuit compresses data to produce compressed data and transmits the compressed data through the network interface. In response to a decompression request from the processor for compressed data the decompression circuit retrieves the requested compressed data, speculatively detects codewords in each of a plurality of overlapping bit windows within the compressed data, selects valid codewords from some, but not all of the overlapping bit windows, decodes the selected valid codewords to generate decompressed data, and provides the decompressed data to the processor.

Performing parallel deflate compression

The following description is directed to decompression using cascaded history buffers. In one example, an apparatus can include a decompression pipeline configured to decompress compressed data comprising code words that reference a history of decompressed data generated from the compressed data. The apparatus can include a first-level history buffer configured to store a more recent history of the decompressed data received from the decompression pipeline. The apparatus can include a second-level history buffer configured to store a less recent history of the decompressed data received from the first-level history buffer.

Growing community of inventors

Tel Aviv, Israel

Ori Weber