Intel Corporation

Ori Lempel

Zeev Sperber

Naveen Kumar

Naveen Neelakantam

David J Sager

H Peter Anvin

Stanislav Shwartsman

Shlomo Raikin

David Pardo Keppel

Adi Yoaz

Sebastian Winkel

Evgeni Krimer

Michael Neilly

Nirajan L Cooray

Omer Golz

A processor includes a processor core to execute a first translated instruction translated from a first instruction stored in first page of a memory. The processor also includes a translation indicator agent (XTBA) to store a first translation indicator that is read from a physical map (PhysMap) in the memory. In an embodiment, the first translation indicator is to indicate whether the first page has been modified after the first instruction is translated. Other embodiments are described as claimed.

Handling of binary translated self modifying code and cross modifying code

Methods and apparatus relating to a hardware move elimination and/or next page prefetching are described. In some embodiments, a logic may provide hardware move eliminations based on stored data. In an embodiment, a next page prefetcher is disclosed. Other embodiments are also described and claimed.

Tracking mechanism coupled to retirement in reorder buffer for indicating sharing logical registers of physical register in record indexed by logical register

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Ramot Menashe, Israel

Ori Lempel