Philips Electronics North America Corporation

Ori K Mizrahi-Shalom

Neil Edward Birns

Farrell Lynn Ostler

Gregory K Goodhue

Kung-Ling Ko

Claus D Grzyb

A microcontroller with a page zero mode where a memory address space is restricted to one page of a multiple page address space to produce improved performance. Address mapping logic and memory segment selection logic limits addresses to the least significant 16 bits of a possible 24 bit address. Different or alternate microcode program controlled instruction sequences with eliminated high order address clock cycles are used in the page zero mode.

Microcontroller having a page address mode

A microcontroller that provides an environment to run processes developed to run on several prior or low end generation machines with the independent register, status and data space needed for execution, that is, the resources of the microcontroller are a superset of the resources of the prior generation machine. The ability to limit one process from accessing the data space of another independent process is provided by data space segmentation controlled by upper order address bits not accessible by the independent processes. The separate workspaces are configured substantially like a workspace of a prior or low end generation machine allowing the microcontroller to perform the tasks of several independent prior or low end generation machines working in concert.

Microcontroller system for performing operations of multiple

Integrated circuits running with high frequencies are a potential source for RFI (Radio Frequency Interference). To reduce RFI, on-chip dedoupling capacitors are included in the design. To gain maximum advantage of these decoupling capacitors, they should be placed close to drivers and flip-flops. In a standard cell design approach for fabrication of the ICs, capacitors are embedded below the power supply lines. These capacitors are put in special cells, called cap-cells, which are placed by the place and route software on either side of each row of standard cells. Thin oxide capacitors are preferred because they offer the largest capacitance per area. In addition, first and second metal above the capacitor are increased to form thick oxide capacitors that give additional capacitance.

IC standard cell designed with embedded capacitors

An instruction prefetch system for a digital processor, and in particular a microcontroller which includes the prefetch system and instruction queue normally provided as part of the instruction fetch unit, to which is added a second instruction prefetch buffer in the system, preferably in the bus interface unit which serves as the memory interface unit. This added prefetch buffer has storage for only a small number of bytes or words, and operates to supply prefetched instructions to the queue in the instruction fetch unit. However, it operates under the following constraint: it only prefetches within the boundaries of each small block of code memory and stalls when a block boundary is reached until a new address appears. This approach combines some cache and prefetch principles for a limited cost design.

Computer instruction prefetch system

A microcontroller which directly drives a memory with low order address bits during a fetch operation. Driving the low order address bits directly while the high order bits are latched during an address/data multiplex on the same pins allows the latch enable cycle to be skipped during sequential fetches. A sequential address detector indicates when the latch enable cycle can be skipped.

High speed memory access system for a microcontroller with directly

A microcontroller or processor architecture that performs word aligned multi-byte fetches but allows byte aligned instructions. Jump target addresses are word aligned, resulting in a word aligned fetch of the jump-to instruction. An assembler or compiler loads code into an instruction memory with branch instruction target addresses aligned on word boundaries. Returns from interrupts load the program counter with a complete return address which is byte aligned.

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San Jose, CA, United States of America

Ori K Mizrahi-Shalom