Freescale Semiconductor,inc.

Nxp Usa, Inc.

Ori Goren

Avraham Horn

Roy M Shor

John J Vaglica

Roi Menahem Shor

Amit Gur

Odi Dahan

Tuongvu Van Nguyen

Yaron Netanel

Arvind Kaushik

Somvir Dahiya

Aviel Livay

Gil Moran

Arindam Sinha

Shay Shpritz

Nir Baruch

Dror Gilad

Yehuda Shvager

Yossy Neeman

Alon Shoshani

Yael Kahil

Gad Yuval

Avraham Rabinovich

Puneet Wadhawan

Roy Shor

Interfacing between radio units in a base station in a mobile communication system uses a common public radio interface CPRI for streaming IQ data samples and control data arranged in lanes. A separate serial interface sRIO is now additionally used for transferring selected control data arranged in packets to a controller, the selected control data being streamed between other radio units via the common public radio interface. In the radio unit, the selected control data are arranged in packets to be transmitted via the serial interface, and, vice versa, the selected control data arranged in packets received via the serial interface are arranged in lanes to be streamed. Advantageously the control data of the streaming CPRI interface is seamlessly transferred to the controller via the packet based serial interface.

Method and device for streaming control data in a mobile communication system

Interfacing between radio units in a base station in a mobile communication system uses a common public radio interface CPRI for streaming IQ data samples arranged in lanes. A separate serial interface sRIO is now additionally used for transferring selected data samples arranged in packets, the selected samples corresponding to selected lanes streamed between other radio units via the common public radio interface. In the radio unit, the selected data samples are arranged in packets to be transmitted via the serial interface, and, vice versa, the selected data samples arranged in packets received via the serial interface are arranged in lanes. A system timer coupled to the CPRI generates a timebase for controlling the sRIO interface in order to have it synchronized. Advantageously the data sample transfer capacity of the streaming CPRI interface is extended using the packet based serial interface.

Method and device for data streaming in a mobile communication system

A system for use in nodes communicating over a CPRI (common public radio interface) allows each networking node in a daisychain configuration to seamlessly manage the control and management HDLC (high-speed data link control) channel for both uplink and downlink. The connection is kept alive through a soft reset flow. Received HDLC packets can be extracted for use by a local node. Locally generated packets can be inserted into the packet data stream at the datalink layer for onward transmission over the CPRI. The system arbitrates between the locally generated packet data held in a buffer in the local node and remote packet data received from a remote node and held in the local node in a first in first out buffer for onward transmission to a subsequent node after arbitration. Remote packet data is given priority.

Apparatus, system and method for controlling packet data flow

A processor device processes data samples of a radio signal in a mobile communication system. A fast flow process is executed for all samples and a batch process is executed at intervals on a subset of the samples. The device has a processor for executing the flow process via a local buffer memory, a memory interface to a system memory, and a memory controller for controlling storing of the data samples in the buffer memory. The processor establishes whether data samples in the local buffer memory are part of the subset, and if not, invalidates them after executing the flow process. The memory controller provides free memory space in the local buffer by transferring data samples which are not invalidated from the local buffer memory to the system memory, and by invalidating processed samples. Advantageously the local buffer may be relatively small, while the amount of data transferred to the system memory is limited.

Device and method for processing in a mobile communication system

A Common Public Radio Interface, CPRI, lane controller of a processor, in a Time Division Duplex, TDD, system, said CPRI lane controller comprising: a Direct Memory Access (or more than one), DMA, controller connected to a memory through a switch fabric to perform read or/and write memory access transactions via an internal system bus of said processor, wherein said DMA controller is adapted to generate a RX/TX transaction interrupt(s) for each completed memory access RX/TX transaction counted by a corresponding transaction counter(s) which provides a TDD slot awareness interrupt(s) when a RX/TX TDD slot has terminated, wherein said DMA controller has a steering control(s) adapted to steer the memory access transactions either to said memory or to be legitimately blocked by said switch fabric in response to said TDD slot awareness interrupt(s) to save bandwidth, BW, of the internal system bus of said processor.

Common public radio interface (CPRI) lane controller coupled to direct memory access (DMA) wherein a time division duplex (TDD) steers control of CPRI

Interfacing according to a common public radio interface in a base station in a mobile communication system is described. The interfacing comprises a conversion process for rate-converting legacy data samples. First a predetermined number of the legacy data samples is converted to frequency samples in a frequency domain, then the frequency samples are zero padded to extend the frequency range according to a related sample rate of a 4G data format and then converted into a number of data samples of the related sample rate. The related sample rate is a multiplication of S/K times a basic frame rate of the 4G data format, S samples being allocated to K frames, K and S being integers and K being 8 or less. Advantageously large buffers for allocating a large number of legacy samples to 4G frames are avoided.

Method and device for interfacing in a mobile communication system

An apparatus for facilitating the re-distribution of processing load between a plurality of radio equipment controllers arranged in a daisy chain configuration on a Common Public Radio Interface. The apparatus may be included in each REC and has two framers which may co-operate to forward IQ data of antenna carriers received on a downlink from a preceding REC to a subsequent REC in the chain and a DMA module or channel which can read IQ data from a system memory for onward transmission. In a re-allocation mode, the framer may be reconfigured so that an AxC initially allocated to a preceding REC for processing may be instead, accessed by a second (usually redundant) transmit DMA module included in the apparatus from system memory and transferred to the framer for onward transmission.

Method and apparatus for processing data flows

A controller device can control the time of a slave sub-system in a chain in a base station system. The controller device comprises a slave transceiver for receiving/transmitting from/to a master sub-system, and a synchronization device for synchronizing a clock of the slave transceiver to a clock of the master sub-system based on the received signal received from the master sub-system. The synchronization circuitry comprises a clock input port for receiving an external clock signal from an external clock generator. At a received signal input port the received signal can be received from the master transceiver. A tracking loop couples the received signal input and the second phase input to a control input of a controllable PLL, for providing a negative feedback which controls a phase and/or frequency of the feedback signal to counter the phase and or frequency error between the external clock signal and the received signal.

Synchronization circuitry, common public radio interface enable device, and a method of synchronizing a synchronized clock signal of a second transceiver to a clock of a first transceiver

A digital signal processor (), compatible with the Common Public Radio Interface (CPRI), permits reading and writing of IQ data of antenna carriers which have two different sampling rates by using just two single sample rate DMA (Direct Memory Access) modules (). The digital signal processor () is capable of processing data of different sampling rates on just one CPRI lane comprising one framer (). This is achieved by incorporating a divider module () and a multiplexer module () between the framer () and system memory (). The processor () may also be configured so that single sampling rates can also be accommodated.

System and method for processing data flows

A method and apparatus automatically controls the insertion of information flow data over a shared CPRI link () by providing a hardware control mechanism (-) at a local radio base station subsystem () connected in a CPRI daisy chain configuration between a downstream RE device () and an upstream REC device () for determining whether the control word being transmitted is sourced from a downstream device (e.g., forwarded data from a downstream RE device) or from the local device.

Method and system for automatically controlling the insertion of control word in CPRI daisy chain configuration

The method and system supports multiple bandwidth traffic over a single CPRI (common public radio interface) link () using a single bandwidth DMA (direct memory access) engine () and fast Fourier transform/inverse fast Fourier transform processing. () The invention exploits fast Fourier transform/inverse fast Fourier transform properties and is particularly suitable for supporting LTE (Long Term Evolution) cellular communication systems () The CPRI Media Access Control is configured in each CPRI lane to run at the maximum bandwidth among the bandwidths required. In the uplink, lower bandwidth data samples are padded with zeros and flexible positioning may be used to arrange the data in a CPRI frame. In the downlink, the radio equipment receiver () only processes the relevant data and ignores any interpolated samples. The invention is compatible with CPRI and LTE standards.

Processing data flows over a single common public radio interface

Interfacing between radio units in a base station in a mobile communication system may use synchronized clocks. A controller device has a tracking clock circuit for generating a transmit clock, the tracking clock circuit comprising a clock input for receiving a reference clock and a sync input for receiving an external synchronization signal. A multiplying phase locked loop generates the transmit clock in dependence on the reference clock and a divider output of a controllable divider coupled to the transmit clock. A tracking loop has a phase detector coupled to the sync input and the divider output for detecting a phase error between the external synchronization signal and transmit clock, and a phase control circuit for generating a phase control signal based on the phase error, the phase control signal being coupled to a control input of the controllable divider for adapting the division function.

Device and method for synchronization in a mobile communication system

A device includes a first memory unit adapted to store encrypted instructions, a processor adapted to execute decrypted instructions, a second memory unit accessible by the processor, and a decryption unit. The device includes a key database and a key selection circuit, wherein the key selection circuit is adapted to select a selected decryption key from the key database for decrypting encrypted instructions. The selection is responsive to a fixed selection information stored within the integrated circuit and to received key selection information. A method includes a stage of receiving encrypted instructions; and executing decrypted instructions by a processor. The method includes receiving key selection information, selecting a selected decryption key out of a key database in response to fixed selection information and to the received key selection information, and decrypting encrypted instructions using the selected decryption key.

Device and method for securing software

A device and a method, the device has transaction scheduling capabilities, and includes: (i) a memory unit adapted to output data at a first data rate, (ii) a data transaction initiator adapted to receive data at a second data rate that is lower than the first data rate; (iii) a deep pipelined crossbar characterized by a latency; and (iv) a data rate converter connected between the deep pipelined crossbar and the data transaction initiator; wherein the data rate converter is adapted to schedule a transaction of data unit from the memory unit in response to the latency of the deep pipelined crossbar, the first data rate, the second data rate, and size of an available storage space, within the data rate converter allocated for storing data from the memory unit.

Device and method for scheduling transactions over a deep pipelined component

A method for designing an interconnect, the method includes determining an amount of input ports, an amount of output ports; characterized by selecting multiple modular components such as to form an interconnect, whereas each modular component is selected from a group of modular components that are verified by parametric verification environment. An interconnect that includes multiple input ports and multiple output ports, characterized by including multiple modular components; whereas each modular component is adapted to support a certain point-to-point protocol; whereas at least one modular component includes a sampling circuit and a bypass circuit, whereas the sampling circuit is selectively bypassed by the bypass circuit.

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Kibutz Ruchama, Israel

Ori Goren