International Business Machines Corporation

Orest Bula

Edward W Conrad

William C Leipold

Daniel C Cole

James Allan Bruce

Michael Straight Hibbs

Joshua J Krueger

Garrett Stephen Koch

Richard S Gomez

Justin A Woyke

David V Horak

Steven J Holmes

Jed Hickory Rankin

Robert K Leidy

John Maxwell Cohn

Ning Lu

Paul A Rabidoux

Timothy E Neary

Donald J Samuels

Archibald John Allen

Emily E Fisch

Stephen E Knight

An automated system for analyzing mask defects in a semiconductor manufacturing process is presented. This system combines results from an inspection tool and design layout data from a design data repository corresponding to each mask layer being inspected with a computer program and a predetermined rule set to determine when a defect on a given mask layer has occurred. Mask inspection results include the presence, location and type (clear or opaque) of defects. Ultimately, a determination is made as to whether to scrap, repair or accept a given mask based on whether the defect would be likely to cause product failure. Application of the defect inspection data to the design layout data for each mask layer being inspected prevents otherwise acceptable wafer masks from being scrapped when the identified defects are not in critical areas of the mask.

Mask defect analysis system

A method and structure for creating a photomask data set includes inputting a design data set, creating a simulated printed data set by applying a lithography simulation model to chosen levels of the design data set, merging each chosen level of the design data set with each corresponding level of the simulated printed data set in order to produce a merged design data set, applying at least one test to the merged design data set, correcting the design data set based on results of the test to produce a corrected design data set, repeating the creating of the simulated printed data, merging, applying the test and correcting using the corrected design data set until the corrected design data set passes the test, and outputting the corrected design data set as the photomask data set.

Interactive optical proximity correction design method

A method and structure for a photomask that includes a substrate having a first transmittance, a first pattern to be transferred to a photosensitive layer (the first pattern having a second transmittance lower than the first transmittance) and a second pattern having a third transmittance greater than the second transmittance and less than the first transmittance. The second pattern is adjacent at least a portion of the first pattern, and the substrate and the second pattern transmit light substantially in phase.

Method to control nested to isolated line printing

An assist feature is formed on a lithographic reticle or mask using a hybrid resist and an exposure dose such that only an annular area is effectively exposed having a width that is potentially less than the minimum feature size that can be resolved by the mask exposure tool to simultaneously or sequentially form both a feature of interest and an assist feature for enhancing imaging of the feature of interest when the feature is printed to a wafer. Since the assist feature can be imaged simultaneously with the feature of interest or multiple assist features imaged concurrently, possibly between closely spaced features, data volume and mask writing time are greatly reduced. The invention is particularly applicable to the scaling of contact holes for connections to active devices in extremely high density integrated circuits.

Assist features for contact hole mask patterns

A control target structure and method for monitoring the lithographic affects on minimum feature in a lithographic process. The control target uses line array elements having a nominal width. By changing the shape of the line-ends of the elements the control target can be optimized for controlling either focus or dose.

Structure for lithographic focus control features

Method for effecting edge bias correction of topography-induced linewidth variations which are encountered in printed or integrated circuits on substrates or semiconductor devices for electronic packages. The method modifies data for current levels which is predicated on prior level data and models, as to the manner in which topography will affect the resist and/or antireflective coating (ARC) thicknesses, so as to improve upon linewidth (LW) control and, in general, imparting improved processing windows. The method can be implemented in the form of computer-executable instructions which are embodied in one or more program modules stored on computer-usable media.

Method for edge bias correction of topography-induced linewidth variation

A structure for a semiconductor chip which includes a first region having first cells for storing and processing data, and a second region outside the first region having OPC structures, wherein the OPC structures comprise decoupling capacitors. The line widths of the active gates of first cells are the same size or similar in size as the OPC structures. The OPC structures reduce proximity effects of active devices in the first cells, and comprise N-type FETs and P-type FETs, that are located in the second region. The OPC structures may have a width greater than the first cells. The second region can be multiple OPC structures, whereby the second region comprises multiple decoupling capacitors. The active devices in the first cells are separated by a first distance and the OPC structures are separated from the active devices by the first distance.

Optical Proximity Correction Structures Having Decoupling Capacitors

A method and computer system are provided for checking integrated circuit designs for design rule violations. The method may include generating a working design data set, creating a wafer image data set, comparing the wafer image data set to the design rules to produce an error list and automatically altering the working design data set when the comparing indicates a design rule violation. The method further automatically repeats the creating, the comparing and the automatically altering until no design rule violations occur or no solution to the errors exists.

Auto correction of error checked simulated printed images

A method for including etch bias corrections in pre-processing of integrated circuit design data to compensate for deviations introduced during lithographic printing and etching. The design data is segmented, and etch bias corrections are applied to the segments based on their proximity to adjacent design features. Adjusted or corrected design data is produced which may be used to create a mask which includes etch bias corrections for better fidelity and reproduction of the original design in the etching step. Etch bias corrections may also be applied based upon characteristics of regions defined in the design, or on a pattern density of the design.

Method of etch bias proximity correction

Fine feature lithography is enhanced by selectively providing exposures to correct for effects such as foreshortening, corner rounding, nested to isolated print bias, feature size dependent bias, and other image biases in semiconductor processing. These results are achieved by increasing the local exposure dose in critical areas of specific images, such as line ends and corners. The general process incorporates techniques which tailor the exposure dose as a function of position to achieve the desired final image shape. The techniques include contrast enhancement layers (CEL), scanning optical beams, and exposures with different masks. In one embodiment the process of forming a pattern comprises the steps of providing a substrate having a photosensitive coating, exposing the center area of the pattern on the photosensitive coating with one mask, and exposing ends of the pattern on the photosensitive coating without exposing the center area with a second mask. The second exposure overlaps the first exposure and may extend beyond the pattern but the second dose is much lower than the first dose.

Process for enhanced lithographic imaging

A structure and method for checking semiconductor designs for design rule violations includes generating a predicted printed structure (i.e., an ideal image) based on the semiconductor designs, altering the ideal image to include potential manufacturing variations, thereby producing at least two production images representing different manufacturing qualities, and comparing the production images to the design rules to produce an error list.

Error checking of simulated printed images with process window effects included

The distribution of ultraviolet light irradiated from an illumination source to optical elements of a projection exposure device is varied by an illumination aperture. The illumination aperture is formed with a plurality of openings which may be opened or closed independently to the passage of irradiating light. The size and shape of the opening formed by the plurality of openings of the illumination aperture is determined according to the particular image to be projected.

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Shelburne, VT, United States of America

Orest Bula