Marvell Israel (misl) Ltd.

Other

Marvell International Limited

Oren Shafrir

Erez Izenberg

Dimitry Melts

Erez Amit

Ruven Torok

Eitan Joshua

Hunglin Hsu

Chia-Hung Chien

Systems and methods described herein provide for communicating an addressable request from cache circuitry to a cache memory. The addressable request is received at a hardware bridge coupled to the cache circuitry and is directed to the cache memory, wherein the cache memory includes a direct memory access (DMA) memory and a programmable input/output (PIO) memory operable within a same address space of the cache circuitry. A service command associated with the addressable request is sent from the hardware bridge to a microcontroller. In response to receiving the service command, the microcontroller activates the PIO memory by: 1) transferring write data from an on-die memory to the PIO memory when the service command is a write command, and 2) transferring read data from the PIO memory to the on-die memory when the service command is a read command.

Systems and methods for communicating addressable requests to a programmable input/output memory over a hardware bridge

Aspects of the disclosure provide a circuit that includes a first memory, a second memory and a comparator. The first memory is configured to store a plurality of values corresponding to a first plurality of ranges and generate an output value in response to a lookup key. The output value is indicative of the lookup key matching a stored value corresponding to a first range in the first plurality of ranges. The second memory is configured to store limiting values of a second plurality of ranges, and output a set of limiting values for a second range in association with the first range based on the output value of the first memory. The comparator is configured to compare the input value with the set of limiting values to determine whether the second range is inclusive of the lookup key.

Method and apparatus for multi-range look-up

Systems and methods are provided for a hardware-implemented multi-buffer. A system includes a buffer memory comprising a shared memory space, where the memory space is shared between a first buffer and a second buffer, and where a dynamic delineation of the memory space between the first buffer and the second buffer is identified by a divider address. A dynamic buffer control circuit includes a control memory that is configured to store the divider address, a first memory utilization metric associated with the first buffer, and a second memory utilization metric associated with the second buffer. A system further includes one or more comparator circuits configured to compare the first memory utilization metric and the second memory utilization metric, where the dynamic buffer control circuit changes the divider address based on the comparison.

Method and apparatus for automated division of a multi-buffer

A data unit is received, wherein the data unit includes a primary information data structure and a primary redundancy data structure. A secondary error correction operation is performed on one or more selected fields within the primary information data structure. After performing the secondary error correction operation, a primary error correction operation is performed on the data unit using the primary redundancy data structure, the primary error correction operation separate from the secondary error correction operation.

Method and apparatus for enhanced error correction

A data unit is received, wherein the data unit includes a primary information data structure and a primary redundancy data structure. A field in the primary information data structure is detected. A secondary error correction operation is performed on the detected field. After performing the secondary error correction operation, a primary error correction operation is performed on the data unit using the primary redundancy data structure.

In accordance with the teachings described herein, systems and methods are provided for performing forward error correction. A decoder for performing forward error correction for a frame in a data stream includes a state machine configured to determine if a code block within the frame received by the decoder is a complete code block or a partial code block, the frame including a plurality of code blocks. A decoding unit is configured to receive the code block, and, when the code block is a partial code block, to generate an output based on decoding the partial code block and an additional partial decoding result that is input to the decoding unit.

Growing community of inventors

Tel Aviv, Israel

Oren Shafrir