Intel Corporation

Oren Lamdan

Efraim Rotem

Varghese George

Sanjeev S Jahagirdar

Jose P Allarey

Alon Naveh

Tomer Ziv

Ofer J Nathan

Nathan Ofer

Ittai Anati

Lev Finkelstein

Guillermo Savransky

Aviad Cohen

For one disclosed embodiment, a processor comprises a plurality of processor cores to operate at variable performance levels. One of the plurality of processor cores may operate at one time at a performance level different than a performance level at which another one of the plurality of processor cores may operate at the one time. The plurality of processor cores are in a same package. Logic of the processor is to set one or more operating parameters for one or more of the plurality of processor cores. Logic of the processor is to monitor activity of one or more of the plurality of processor cores. Logic of the processor is to constrain power of one or more of the plurality of processor cores based at least in part on the monitored activity. The logic to constrain power is to limit a frequency at which one or more of the plurality of processor cores may be set. Other embodiments are also disclosed.

Operating point management in multi-core architectures

With the progress toward multi-core processors, each core is can not readily ascertain the status of the other dies with respect to an idle or active status. A proposal for utilizing an interface to transmit core status among multiple cores in a multi-die microprocessor is discussed. Consequently, this facilitates thermal management by allowing an optimal setting for setting performance and frequency based on utilizing each core status.

Method, apparatus, and system for optimizing frequency and performance in a multidie microprocessor

For one disclosed embodiment, a processor comprises a plurality of processor cores to operate at variable performance levels. One of the plurality of processor cores may operate at a performance level different than a performance level at which another one of the plurality of processor cores may operate. Logic of the processor is to monitor activity of one or more of the plurality of processor cores. Logic of the processor is to constrain power of one or more of the plurality of processor cores based at least in part on the monitored activity. Other embodiments are also disclosed.

For one disclosed embodiment, a plurality of processor cores of a multicore processor may be operated at variable performance levels. One processor core may operate at a performance level different than a performance level at which another processor core may operate. Performance levels of multiple processor cores may be identified. Power consumption of the plurality of processor cores may be controlled based at least in part on the identified performance levels. Other embodiments are also disclosed.

Method and apparatus to control power consumption of a plurality of processor cores

Method, apparatus, and system for optimizing frequency and performance in a multi-die microprocessor

Briefly, a processor and a method of estimating an active energy consumption of two or more cores of a processor based on dispatching micro operations to one or more execution units of the processor.

Method and apparatus to estimate energy consumed by central processing unit core

A method, system, and apparatus to enable at least one active core in a multi-core processor to operate at a higher operating point while at least one other core in the multi-core processor is in an idle state. When the idle core exits the idle state, the operating point may be reduced after a hysteresis timer has expired.

Method, apparatus, and system for increasing single core performance in a multi-core microprocessor

Systems and methods of managing operating points provide for determining the number of active cores in a plurality of processor cores. A maximum operating point is selected for at least one of the active cores based on the number of active cores. In one embodiment, the number of active cores is determined by monitoring an ACPI processor power state signal of each of the plurality of cores.

Method, system, and apparatus for selecting a maximum operation point based on number of active cores and performance level of each of the active cores

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Kiryat Tivon, Israel

Oren Lamdan