Broadcom Corporation

Oren David

Eli Aloni

Gilad Ayalon

A reduced instruction set computer (RISC) includes at least one arithmetic logic units (ALUs), which are arranged to evaluate logical conditions. A processing pipeline is arranged to solve a decision problem that is representable as a decision tree including at least three nodes by processing a sequence of pipelined instructions that traverse the decision tree. At least some of the pipelined instructions instruct the one or more ALUs to evaluate respective logical conditions, such that the pipeline flushes the instructions from the pipeline no more than once in the course of processing the sequence regardless of whether the logical conditions evaluate to true or false.

High speed multi-threaded reduced instruction set computer (RISC) processor

A reduced instruction set computer (RISC) processor includes a processing core, which is arranged to process a software thread. A hardware-implemented scheduler is arranged to receive respective contexts of a plurality of software threads, to determine a schedule for processing of the software threads by the processing core, and to serve the contexts to the processing core in accordance with the schedule.

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Kfar Sava, Israel

Oren David