Western Digital Technologies, Inc.

Sandisk Il Ltd.

Sandisk Technologies Inc.

Opher Lieber

Ariel Navon

Shay Benisty

Alexander Bazarsky

Menahem Lasser

Eran Sharon

Itshak Afriat

Idan Alrod

Rotem Sela

Amir Shaharabany

Mark Shlick

David Chaim Brief

Yoav Markus

Ofer Shapira

Idan Alord

Izhak Afriat

A method and apparatus for cache management and eviction polices using unsupervised reinforcement learning schemes is disclosed.

Solid state drive cache eviction policy by an unsupervised reinforcement learning scheme

Data may be read from a data storage device using host performance booster (HPB). An encoded HPB entry in a read command provides the PBA (Physical Block Address) as well as the run length. The LBA (Logical Block Address), PBA, and run length are placed in an HPB read buffer table. The HPB read buffer table is located in the host device. When the read command is received by the data storage device, the data storage device reads the LBA, transfer length, and HPB entry from the read command. The HPB entry contains the PBA for the LBA as well as the run length for the data to be read. For non-sequential reads, the HPB contains the LBA, transfer length, and reference to a write buffer table that is stored in the data storage device.

Boosting reads of chunks of data

Aspects of the disclosure provide for distributed flash interface module (FIM) processing in a solid state drive (SSD). Methods and apparatus lock a queue and retrieve a command from the queue. The command indicates an operation to be executed in conjunction with one or more non-volatile (NVM) dies of the SSD. The methods and apparatus then lock a NVM interface corresponding to the one or more NVM dies, determine whether the operation is a transfer operation, and execute the operation using the locked NVM interface according to whether the operation is the transfer operation. When the operation is determined to be the transfer operation, the queue is unlocked to allow execution of a second operation from the queue by a second controller in parallel with the operation executed by the controller. Thereafter, the NVM interface is unlocked after execution of the operation is complete.

Distributed flash interface module processing

A memory system or flash card may include an algorithm or process for managing the handling of large tables in memory. A delta may be used for each table to accumulate updates. There may be a plurality of deltas for a multi-level delta structure. In one example, the first level delta is stored in random access memory (RAM), while the other level deltas are stored in the flash memory. Multiple-level deltas may improve the number of flash writes and reduce the number and amount of each flush to the actual table in flash. The use of multi-level deltas may improve performance by more efficiently writing to the table in flash.

Multi-level table deltas

A flash memory system that uses repeated writing of the data to achieve stable storage, is adapted for efficient cache flushing operations by utilizing a part of the non-volatile flash memory array as a designated buffer for the data, in which data integrity is retained until all repeat writing thereof is complete. Repeated writing is carried out from the designated buffer directly to the final storage locations in the flash memory array, for example using simple internal copy back operations.

Flash cache flushing method and system

Data is received at a computer memory to be programmed in single-level-cell mode. A stress level of a first section of the computer memory is determined. A stress level of a second section of the computer memory is determined. The stress levels of the first and second sections of the computer memory are compared to determine which one of the first and second sections is a less stressed single-level-cell mode section of the computer memory. The data received at the computer memory is programmed in the less stressed single-level-cell mode section of the computer memory.

Methods for balancing write operations of SLC blocks in different memory areas and apparatus implementing the same

Systems and methods for performing defect detection and data recovery within a memory system are disclosed. A controller of a memory system writes data to a physical location of a memory and stores the physical location of the memory in a Flash Management Unit Tag cache ('Tag cache'). The controller identifies a data keep cache that is associated with the physical location of memory and updates an XOR sum stored in the identified data keep cache. The controller determines whether to perform a verification operation, and in response to a determination to perform the verification operation, verifies data stored at each physical location that has been stored in the Tag cache since a previous verification operation. Additionally, the controller determines whether to perform a reset operation, and in response to a determination to perform the reset operation, flushes the Tag cache and the plurality of data keep caches.

Systems and methods for performing data recovery in a memory system

A data storage device includes a controller and a non-volatile memory coupled to the controller. The non-volatile memory includes executable boot code that is executable by a processor associated with the data storage device. The controller is configured to read a first portion of the executable boot code from a first region of the non-volatile memory, and in response to detecting a condition, move a second portion of the executable boot code in a second region of the non-volatile memory to a third region of the non-volatile memory.

Moving executable code from a first region of a non-volatile memory to a second region of the non-volatile memory to reduce read disturb

Methods, apparatus and computer medium for enforcing one or more cache management policies are disclosed herein. In some embodiments, a flash memory of a storage device includes a plurality of flash memory dies each flash memory die including a respective cache storage area and a respective main storage area. A determination is made, for data that is received from an external host device to which main storage area the received data is addressed thereby specifying one of the plurality of flash memory dies as a target die for the received data. Whenever the received data is written into a cache storage area before being written into a main storage area, the received data is written into the cache storage area of the specified target die.

Method and apparatus for enforcing a flash memory caching policy

Data stored in memory is decoded using iterative probabilistic decoding and multiple decoders. A first decoder attempts to decode a representation of a codeword. If the attempt is unsuccessful, a second decoder attempts to decode the representation of a codeword. The second decoder may have a lower resolution than the first decoder. Probability values such as logarithmic likelihood ratio (LLR) values may be clipped in the second decoder. This approach can overcome trapping sets while exhibiting low complexity and high performance. Further, it can be implemented on existing decoders such as those used in current memory devices.

Low density parity code (LDPC) decoding for memory with multiple log likelihood ratio (LLR) decoders

A method and system for balancing host write operations and cache flushing is disclosed. The method may include steps of determining an available capacity in a cache storage portion of a self-caching storage device, determining a ratio of cache flushing steps to host write commands if the available capacity is below a desired threshold and interleaving cache flushing steps with host write commands to achieve the ratio. The cache flushing steps may be executed by maintaining a storage device busy status after executing a host write command and utilizing this additional time to copy a portion of the data from the cache storage into the main storage. The system may include a cache storage, a main storage and a controller configured to determine and execute a ratio of cache flushing steps to host write commands by executing cache flushing steps while maintaining a busy status after a host write command.

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Kfar Saba, Israel

Opher Lieber