Intel Corporation

Opher D Kahn

Altug Koker

Thomas A Piazza

Robert L Farrell

Zeev Offen

Ariel Berkovits

Jeffrey R Wilcox

Robert Valentine

Andrew F Glew

Richard A Uhlig

Alon Naveh

Alexander D Peleg

Ronny Ronen

Bob Valentine

Maury J Bach

Erez Birenzwig

Gad Shlomo Sheaffer

Adi Yoaz

Doron Orenstein

Ilan Y Spillinger

A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

Technique to share information among different cache coherency domains

A processing system includes a bus and a processor whose core is constrained to have one or more core clock signal frequencies no lower than a predetermined multiple of the lowest of one or more bus clock signal frequencies. In a power-save mode, the processor is able to generate one or more core clock signals at frequencies such that the lowest core clock signal frequency is lower than the predetermined multiple of the lowest of the one or more bus clock signal frequencies in performance mode. The processor is able to achieve this by generating the one or more bus clock signals so that the lowest of the bus clock signal frequencies in power-save mode is lower than the lowest of the bus clock signal frequencies in performance mode.

Reducing CPU and bus power when running in power-save modes

Apparatus and methods to adaptively throttle accesses to memory employ a masking tool to specify the percentage of memory bandwidth available for access. The apparatus applies the mask and monitors the number of memory accesses during a throttle-monitoring window. If the number of memory accesses during the throttle-monitoring window exceeds or is fewer than the percentage of memory bandwidth specified by the mask, access to the memory continues until the end of the throttle-monitoring window and at the end of the throttle-monitoring window the apparatus selects the next lower mask for a lower memory bandwidth allocation or selects the next higher mask for a higher memory bandwidth allocation, respectively.

Adaptive throttling of memory accesses, such as throttling RDRAM accesses in a real-time system

According to an embodiment of the present invention, a microprocessor includes an expanded logical register set that can be accessed by instructions including legacy opcodes and remapped addressing mode information. The known IA-32 instruction set is limited to accessing eight logical general integer registers. An IA-32 instruction can specify which of the eight logical general integer registers are to be accessed via 3-bit register identifier fields of the addressing mode information of the instruction. Each 3-bit register identifier can specify any of the eight logical general integer registers. An expanded logical register set (e.g., sixteen logical registers, thirty-two logical registers, sixty-four logical registers, etc.) can be accessed by remapping the addressing mode information to include at least four-bit register identifiers without defining new opcodes or defining additional instruction prefixes.

Method and apparatus to support an expanded register set

A circuit includes a switch unit, an non-protected register and a set of protected control registers. The set of protected control registers stores safe data for use by another unit of the circuit. The switch unit outputs the data stored by one of the set of protected control registers as a function of the data stored by the non-protected register. The data in the non-protected register can be changed by software in response to user input, operational mode or other condition or conditions.

Method and apparatus for software selection of protected register settings

A method and apparatus for resuming operations from a low latency wake-up low power state. One embodiment provides a system including a processor, an operating system, and a memory subsystem that requires initialization commands to exit a memory low power state. Control logic detects exit from an operating system low latency low power state and responsively generates a plurality of initialization commands to remove the memory subsystem from the memory low power state prior to deasserting a stop clock signal and allowing execution to resume.

Method and apparatus for resuming memory operations from a low latency wake-up low power state

A memory controller (MC) includes a buffer control circuit (BCC) to enable/disable buffer coupled to a terminated bus. The BCC can detect transactions and speculatively enable the buffers before the transaction is completely decoded. If the transaction is targeted for the terminated bus, the buffers will be ready to drive signals onto the terminated bus by the time the transaction is ready to be performed, thereby eliminating the 'enable buffer' delay incurred in some conventional MCs. If the transaction is not targeted for the terminated bus, the BCC disables the buffers to save power. In MCs that queue transactions, the BCC can snoop the queue to find transactions targeted for the terminated bus and begin enabling the buffers before these particular transactions are fully decoded.

Low latency buffer control system and method

Growing community of inventors

Zichron-Yacov, Israel

Opher D Kahn