Solar Junction Corporation

Intel Corporation

Onur Fidaner

Michael West Wiemer

Ewelina Natalia Lucow

Vijit A Sabnis

Ting Liu

Jun-Fei Zheng

Homan Bernard Yuen

Vijit Sabnis

Pranob Misra

Paul F Lamarche

Michael J Sheldon

Lan Zhang

Daniel Derkacs

David Andrew Barclay Miller

Hilmi Volkan Demir

A single-step wet etch process is provided to isolate multijunction solar cells on semiconductor substrates, wherein the wet etch chemistry removes semiconductor materials nonselectively without a major difference in etch rate between different heteroepitaxial layers. The solar cells thus formed comprise multiple heterogeneous semiconductor layers epitaxially grown on the semiconductor substrate.

Method for etching multi-layer epitaxial material

A multi junction solar cell is provided with a non-alloyed ohmic contact metallization stack by inversion of the top semiconductor layer from n-type to p-type and including the utilization of a tunnel junction. Alternatively, the non-alloyed ohmic contact can be achieved by changing the top semiconductor layer from a higher bandgap material to a lower bandgap material.

Non-alloyed contacts for III-V based solar cells

The present disclosure provides multi-junction solar cell structures and fabrication methods thereof that improve electrical testing capability and reduce chip failure rates. In the present invention a special masking pattern is used in the layout such that all or some of the epitaxial layers are etched away in the corner areas of each solar cell. Consequently, the semiconductor substrate or one or more of the interconnections between junctions become accessible from the top (the side facing the sun) to make electrical connections.

Methods and apparatus for identifying and reducing semiconductor failures

A semiconductor light detection device fabrication technique is provided in which the cap etch and anti-reflection coating steps are performed in a single, self-aligned lithography module.

Method for making semiconductor light detection devices

Methods in accordance with the present invention provide a quasi-planarized surface between one or more semiconductor devices and at least a portion of surrounding passivation material, where the devices have different elevations above a substrate. A hard mask defines the planarized surface as the interface between the hard mask and both the passivation layer and the device, after a passivation layer etching process. The resulting planarized surface has a small to zero step height, is insensitive to passivation layer non-uniformity and etch non-uniformity, provides full passivation of the device side wall, provides protection for the device against etch-induced damage, and prevents the detrimental effects of passivation layer voids. The methods are applicable to semiconductor device fabrication for electronic and photonic/optoelectronic systems such as, but not limited to, cell phones, networking systems, high brightness (HB) LEDs, laser diodes (LDs), photodiodes, modulator diodes and multifunction solar cells.

Wafer-level quasi-planarization and passivation for multi-height structures

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Stanford, CA, United States of America

Onur Fidaner