Mellanox Technologies, Ltd.

Nvidia Corporation

Omri Kahalon

Gal Shalom

Aviad Shaul Yehezkel

Liran Liss

Adi Merav Horowitz

Ariel Shahar

Avi Urman

Rabia Loulou

Lior Narkis

Rabie Loulou

Asaf Schwartz

Ilan Pardo

Matty Kadosh

Roni Bar Yanai

Uria Basher

Oren Duer

Eitan Hirshberg

Eliav Bar-Ilan

Yossi Kuperman

Yorai Itzhak Zack

Saar Tarnopolsky

Sayantan Sur

Muhamad Grefat

Yohad Dickman

Maxim Gurtovoy

Najeeb Darawshy

Barak Biber

Omer Cohen

Doron Haim

Liel Yonatan Maman

Sagi Farjun

Adit Ranadive

A method for processing includes receiving a definition of a processing pipeline including multiple sequential processing stages. The processing pipeline is partitioned into a plurality of partitions. The first partition of the processing pipeline is executed on a first computational accelerator, whereby the first computational accelerator writes output data from a final stage of the first partition to an output buffer in a first memory. The output data are copied over a packet communication network to an input buffer in a second memory. The second partition of the processing pipeline is executed on a second computational accelerator using the copied output data in the second memory as input data to a first stage of the second partition.

Disaggregation of processing pipeline

Systems and methods herein are for one or more processing units of a subnet manger (SM) to communicate configuration information with at least one subnet management agent (SMA) that is associated with at least one switch and with a host machine, the configuration information to enable the at least one switch to configure a forwarding table based in part on a mapping of at least one virtual network address to physical network addresses of two or more physical ports of the host machine, and the configuration information to enable the host machine to communicate with other host machines using the at least one switch and the at least one virtual network address.

Link aggregation in InfiniBand networks

Systems and methods herein are for at least one circuit that can determine that a network reference associated with a first network hardware is subject to a network performance degradation in a network, can cause suspension of traffic flow associated with the network reference, can save configuration for at least the network reference at a node associated with the first network hardware, and can cause the configuration to be deployed in a second network hardware so that the network reference that was previously in the first network hardware is provided from the second network hardware to resume the traffic flow.

Hardware supported flow migration

A method includes receiving a network packet into a hardware pipeline of a network device; parsing and retrieving information of the network packet; determining, by the hardware pipeline, a packet-processing action to be performed by matching the information to a data structure of a set of flow data structures; sending, by the hardware pipeline, an action request to a programmable core, the action request being populated with data to trigger the programmable core to execute a hardware thread to perform a job, which is associated with the packet-processing action and that generates contextual data; retrieving the contextual data updated by the programmable core; and integrating the contextual data into performing the packet-processing action.

Programmable core integrated with hardware pipeline of network interface device

Multipathing for session-based remote direct memory access (SRDMA) may be used for congestion management. A given SRDMA session group may be associated with multiple SRDMA sessions, each having its own unique 5-tuple. A queue pair (QP) associated with the SRDMA session group may provide a packet for transmission using the SRDMA session group. The SRDMA session group may enable the packet to be transmitted using any of the associated SRDMA sessions. Congestion levels for each of the SRDMA sessions may be monitored and weighted. Therefore, when a packet is received, an SRDMA session may be selected based, at least, on the weight to enable routing of packets to reduce latency and improve overall system efficiency.

Multipathing with remote direct memory access connections

A network device includes one or more ports, match-action circuitry, and an action processor. The one or more ports are to exchange packets between the network device and a network. The match-action circuitry is to match at least some of the packets to one or more rules so as to set respective actions to be performed, at least one of the actions including a programmable action. The instruction processor is to perform the programmable action by running user-programmable software code. The instruction processor includes architectural registers, one or more of the architectural registers being accessible by the match-action circuitry, and the match-action circuitry is to write into the architectural registers information for performing the programmable action.

Network device with programmable action processing

In one embodiment, a network device, including a network interface to receive packets over a packet data network, and a hierarchical policer to provide queue fairness for a plurality of network flows competing for access to a multiplex network receive queue, and including level one meters to label the received packets, a level two meter to receive at least some of the labeled packets and relabel the at least some labeled packets, and queueing logic add the packets labeled with a first label-type to the multiplex network receive queue and drop the packets labeled with a third label-type.

QOS for multiplex network receive queue

A system for transmitting data is described, among other things. An illustrative system is disclosed to include one or more circuits to perform transmitting message-based data over packets. The circuits are capable of identifying a first message, transmitting a first portion of the first message in a first packet, the first packet including a bit indicating the first packet is message-based, and transmitting an end portion of the first message in a second packet, the second packet including a first bit indicating the second packet is message-based and a second bit indicating the second packet comprises the end portion of the first message.

Systems and methods of message-based packets

Systems and methods enable session sharing for session-based remote direct memory access (RDMA). Multiple queue pairs (QPs) can be added to a single session and/or session group where each of the QPs has a common remote. Systems and methods may query a session ID for an existing session group and then use the session ID with an add QP request to join additional QPs to an existing session. Newly added QPs may share one or more features with existing QPs of the session group, such as encryption parameters. Additionally, newly added QPs may be configured with different performance or quality of service requirements, thereby isolating performance, and permitting true scaling for high performance computing applications.

Session sharing with remote direct memory access connections

Methods and systems provided herein involve extracting an input/output (I/O) operation from a packet received over an I/O pipeline, the I/O operation comprising either a read request to read data from at least one storage device or a write request to write data to the at least one storage device; determining that an address associated with the I/O operation exists in a lookup table that is provided for thin provisioning of the at least one storage device; performing one or more RAID calculations associated with the at least one storage device based on the address and the I/O operation; and accessing the at least one storage device to perform the I/O operation based on the one or more RAID calculations; and second processing component configured to carry out a second set of operations that occur when the address associated with the I/O operation does not exist in the lookup table.

Methods and systems for inter-stack communication for logical volume management

API in conjunction with a bridge chip and first and second hosts having first and second memories respectively. The bridge chip connects the memories. The API comprises key identifier registration functionality to register a key identifier for each of plural computer processes performed by the first host, thereby to define plural key identifiers; and/or access control functionality to provide at least computer process Pperformed by the first host with access, typically via the bridge chip, to at least local memory buffer Mresiding in the second memory, typically after the access control functionality first validates that process Phas a key identifier which has been registered, e.g., via the key identifier registration functionality. Typically, the access control functionality also prevents at least computer process P, performed by the first host, which has not registered a key identifier, from accessing local memory buffer M, e.g., via the bridge chip.

System which provides plural processes in a host with asynchronous access to plural portions of the memory of another host

A network adapter includes a network interface, a host interface and processing circuitry. The network interface is configured to connect to a communication network. The host interface is configured to communicate with a host processor running multiple application programs. The processing circuitry includes one or more bandwidth-control policers, and is configured to receive from the communication network a packet destined to a given application program among the application programs running on the host processor, to associate a bandwidth-control policer with the packet, selected from among the bandwidth-control policers, and to apply the selected bandwidth-control policer to the packet to produce a policer result.

Bandwidth-control policers in a network adapter

A network adapter includes a network interface, a host interface and processing circuitry. The network interface is configured to connect to a communication network. The host interface is configured to communicate with a host processor running multiple application programs. The processing circuitry includes one or more bandwidth-control policers, and is configured to receive from the communication network a packet destined to given application program among the application programs running on the host processor, to associate a bandwidth-control policer with the packet, selected from among the bandwidth-control policers, and to apply the selected bandwidth-control policer to the packet to produce a policer result.

A computer system includes one or more processors, one or more hardware accelerators, and control circuitry. The processors are configured to run software that executes tasks in a normal mode. The accelerators are configured to execute the tasks in an accelerated mode. The control circuitry is configured to receive one or more flows of tasks for execution by the processors and the accelerators, assign one or more initial tasks of each flow for execution by the processors, assign subsequent tasks of each flow for execution by the accelerators, and verify, for each flow, that the accelerators do not execute the subsequent tasks of the flow until the processors have fully executed the initial tasks of the flow.

Growing community of inventors

Yehud, Israel

Omri Kahalon